tag: Fraunhofer EAS

Interaction Of Hard IP And Chip-Package
By Andy Heinig - 08 Nov, 2018 - Comments: 0

Current and future customer-specific circuit development requires an increasing number of different interfaces, such as for memory (DDR3, DDR4, LPDDR3, LPDDR4, etc.), radio interfaces (Bluetooth, NBIoT, etc.) or high-speed LVDS/SERDES interfaces (DisplayPort, Ethernet, USB, etc.). For customer-specific circuit projects, these components are frequently purchased as hard IP because the developmen... » read more

Carmakers To Chipmakers: Where’s The Data?
By Ed Sperling And Susan Rambo - 24 Oct, 2018 - Comments: 0

The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Functional Safety And Requirements Engineering
By Roland Jancke - 11 Oct, 2018 - Comments: 0

Currently, dramatically increasing design costs are being reported for safety-critical applications. This is caused by additional necessary actions to implement and verify functional safety requirements. Such requirements are appearing with a clearly increasing tendency in the area of mobility (automotive, transport, aerospace) as well as in industrial automation and medical technology. In many... » read more

Power Delivery Affecting Performance At 7nm
By Brian Bailey - 11 Oct, 2018 - Comments: 4

Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

Temperature Reduction on a High-Power Thermal Demonstrator
By Fraunhofer IIS/EAS - 10 Oct, 2018 - Comments: 0

High-power applications in microelectronic devices and systems is a crucial and severe issue that may cause elevated thermal and thermomechanical phenomena and finally lead the fabricated system to degradation, limitation of its performance, or even failure and destruction of its features. In specific applications, such as those found in the industry and the automotive sector, the power pro... » read more

Aging In Advanced Nodes
By Ann Mutschler - 17 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Mission Profiles
By Jens Michael Warmuth - 13 Sep, 2018 - Comments: 1

In the field of electronic systems, the mission profile has been one of the key concepts since the start of the scientific examination of the subject of reliability. Its exact meaning varies with time and the industry using it. In particular, over the course of increasing digitalization and networking in the context of IoT and the opportunities resulting from this, the subject of mission profil... » read more

Process Corner Explosion
By Ann Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

Minimizing Chip Aging Effects
By Brian Bailey - 13 Sep, 2018 - Comments: 2

Aging kills semiconductors, and it is a growing problem for an increasing number of semiconductor applications—especially as they migrate to more advanced nodes. Additional analysis and prevention methods are becoming necessary for safety critical applications. While some aspects of aging can be mitigated up front, others are tied to the operation of the device. What can an engineering tea... » read more

Variation In Low-Power FinFET Designs
By Ann Mutschler - 30 Aug, 2018 - Comments: 1

One of the biggest advantages of moving to the a leading edge process node is ultra-low voltage operation, where devices can achieve better performance using less power. But the latest generation process nodes also introduce a number of new challenges due to increased variation that can affect everything from signal integrity to manufacturing yield. While variation is generally well understo... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy