tag: gate all around

FinFETs Give Way To Gate-All-Around
By Lam Research - 18 Nov, 2020 - Comments: 0

When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

Manufacturing Bits: Nov. 17
By Mark LaPedus - 17 Nov, 2020 - Comments: 0

Intel’s gate-all-around FETs At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel is expected to present papers on its efforts to develop gate-all-around transistors. One paper from Intel describes a more conventional gate-all-around transistor technology called a nanosheet FET. Another paper involves a next-generation NMOS-on-PMOS nanoribbon transistor technology. (F... » read more

3D Extraction Necessities For 5nm And Below
By Ruben Molina - 25 Jan, 2018 - Comments: 0

For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based analysis and path based analysis, on-chip variation modeling, delay calculation, evolving library models, etc. During those years I always understood that  parasitic extraction was a crucial element of STA and more impo... » read more

Exploring New Scaling Approaches
By Mark LaPedus - 19 Oct, 2017 - Comments: 0

At the recent SPIE Photomask Technology + Extreme Ultraviolet Lithography 2017 conference, Semiconductor Engineering sat down to discuss semiconductor technology with Tsu-Jae King Liu, the TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences at the University of California at Berkeley. More specifically, Liu discussed some of the new... » read more

How Long Will FinFETs Last? (Part 3)
By Ann Mutschler - 07 Oct, 2015 - Comments: 1

Semiconductor Engineering sat down to discuss how long [getkc id="185" kc_name="FinFET"]s will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22... » read more

How Long Will FinFETs Last?
By Ann Mutschler - 13 Aug, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22865" e_name="Samsung"]; and Vic... » read more

Unraveling The Mysteries At IEDM
By Mark LaPedus - 19 Dec, 2014 - Comments: 0

In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

Manufacturing Bits: Oct. 21
By Mark LaPedus - 21 Oct, 2014 - Comments: 0

Peanut butter and chocolate TEMs Lawrence Livermore National Laboratory, Johns Hopkins University and the National Institute of Standards and Technology (NIST) have developed a new microscopy technology that combines two types of key measurements. The technology, dubbed the dynamic transmission electron microscope (DTEM), captures information about both temperature and the crystal structure... » read more

Executive Insight: Luc Van den hove
By Mark LaPedus - 20 Feb, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss current and future process technology challenges with Luc Van den hove, president and chief executive of Imec. What follows are excerpts of that conversation. SE: The industry is simultaneously working on several new and expensive technologies. This includes extreme ultraviolet (EUV) lithography and the next-generation 450mm wafer size. The indu... » read more

Tunnel FETs Emerge In Scaling Race
By Mark LaPedus - 14 Nov, 2013 - Comments: 2

Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers. In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate... » read more

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