tag: gate-level simulation

Simulation Replay Tackles Key Verification Challenges
By Robert Ruiz - 12 Sep, 2024 - Comments: 0

Simulation lies at the heart of both verification and pre-silicon validation for every semiconductor development project. Finding functional or power problems in the bringup lab is much too late, leading to very expensive chip turns. Thorough simulation before tapeout, coupled with comprehensive coverage metrics, is the only way to avoid surprises in silicon. However, the enormous size and comp... » read more

Know Your Own Power, Early And Accurately
By Taruna Reddy - 11 Feb, 2021 - Comments: 0

By Taruna Reddy and Vin Liao Chip designers have always had to balance timing and area. Everyone wants a design as fast as possible and as compact as possible, but these two goals are usually in conflict. For the last couple of decades, minimal power consumption has been a third goal, often of equal importance. Some of the biggest drivers for the semiconductor industry are battery operated p... » read more

The Week In Review: Design
By Jesse Allen - 01 Jun, 2018 - Comments: 0

Tools Real Intent launched Verix SimFix, an intent-driven verification solution for gate-level simulation (GLS) of digital designs designed to eliminate X-pessimism. SimFix uses mathematical methods to identify conditions under which pessimism can occur, and to determine the correct value when those conditions occur. It then generates files to use in simulation that detect and correct pessimis... » read more

Gate-Level Simulation Methodology
By Cadence - 26 Aug, 2015 - Comments: 0

The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is responsible for longer run times, high memory requirements, and the need for a growing set of gate-level simulation (GLS) applications including design for test (DFT) and low- power considerations. As a result, in order to complete the verification requirements on time, it becomes extr... » read more

Know What To Look For
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

Aren’t We Beyond That?
By Ann Mutschler - 21 Jul, 2011 - Comments: 0

The latest and greatest technologies always get the most attention because they are new and fresh, but gate-level simulation—a long-time workhorse tool—is seeing a small comeback with designers as of late. According to Cadence’s Pete Hardee, even though the industry is spending a lot of time looking ahead to architectural-level power modeling and virtual prototyping, the need for detai... » read more

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