DRAM Test And Inspection Just Gets Tougher


DRAM manufacturers continue to demand cost-effective solutions for screening and process improvement amid growing concerns over defects and process variability, but meeting that demand is becoming much more difficult with the rollout of faster interfaces and multi-chip packages. DRAM plays a key role in a wide variety of electronic devices, from phones and PCs to ECUs in cars and servers ins... » read more

Memory Technologies Key To Advancing AI Applications


Memory is an integral component in every computer system, from the smartphones in our pockets to the giant data centers powering the world’s leading-edge AI applications. As AI continues to rise in reach and complexity, the demand for more memory from data center to endpoints is reshaping the industry’s requirements and traditional approaches to memory architectures. According to OpenAI,... » read more

AI Drives Need For Optical Interconnects In Data Centers


An explosion of data, driven by more sensors everywhere and the inclusion of AI/ML in just about everything, is ratcheting up the pressure on data centers to leverage optical interconnects to speed up data throughput and reduce latency. Optical communication has been in use for several decades, starting with long-haul communications, and evolving from there to connect external storage to ser... » read more

Sweeping Changes For Leading-Edge Chip Architectures


Chipmakers are utilizing both evolutionary and revolutionary technologies to achieve orders of magnitude improvements in performance at the same or lower power, signaling a fundamental shift from manufacturing-driven designs to those driven by semiconductor architects. In the past, most chips contained one or two leading-edge technologies, mostly to keep pace with the expected improvements i... » read more

Preparing For Commercial Chiplets


Experts at the Table: Semiconductor Engineering sat down to discuss the path to commercialization of chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts of tha... » read more

Processor Tradeoffs For AI Workloads


AI is forcing fundamental shifts in chips used in data centers and in the tools used to design them, but it also is creating gaps between the speed at which that technology advances and the demands from customers. These shifts started gradually, but they have accelerated and multiplied over the past year with the rollout of ChatGPT and other large language models. There is suddenly much more... » read more

Generative AI Training With HBM3 Memory


One of the biggest, most talked about application drivers of hardware requirements today is the rise of Large Language Models (LLMs) and the generative AI which they make possible.  The most well-known example of generative AI right now is, of course, ChatGPT. ChatGPT’s large language model for GPT-3 utilizes 175 billion parameters. Fourth generation GPT-4 will reportedly boost the number of... » read more

Solving Memory Mapping Issues with Deep RL (Google)


A technical paper titled "Optimizing Memory Mapping Using Deep Reinforcement Learning" was published by Google DeepMind and Google. Abstract: "Resource scheduling and allocation is a critical component of many high impact systems ranging from congestion control to cloud computing. Finding more optimal solutions to these problems often has significant impact on resource and time savings, red... » read more

Server Design With Pin-Efficient CXL Interface (Georgia Tech)


A new technical paper titled "A Case for CXL-Centric Server Processors" was written by researchers at Georgia Tech. Abstract: "The memory system is a major performance determinant for server processors. Ever-growing core counts and datasets demand higher bandwidth and capacity as well as lower latency from the memory system. To keep up with growing demands, DDR--the dominant processor inter... » read more

Pinpointing Timing Delays Can Improve Chip Reliability


Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

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