Fabs Meet Machine Learning


Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to discuss Moore’s Law and photomask technology. Fujimura also explained how artificial intelligence and machine learning are impacting the IC industry. What follows are excerpts of that conversation. SE: For some time, you’ve said we need more compute power. So we need faster chips at advanced nodes, but cost... » read more

Bugs With Long Tails Can Be Costly Pests


I don’t think Van Gogh was considering high performance computing or server architecture, but he made a lot of sense when he said "great things are done by a series of small things brought together." A series of very small things can, and do, create big things: that’s the fundamental premise of long-tail marketing: Amazon, for one has built a strong business from selling millions of niche i... » read more

The Future Of FinFETs


The number of questions about finFETs is increasing—particularly, how long can they continue to be used before some version of gate-all-around FET is required to replace them. This discussion is confusing in many respects. For one thing, a 7nm finFET for TSMC or Samsung is not the same as a 7nm finFET for Intel or GlobalFoundries. There are a bunch of other nodes being proposed, as well, i... » read more

Foundry Challenges in 2018


The silicon foundry business is expected to see steady growth in 2018, but that growth will come with several challenges. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC are migrating from the 16nm/14nm to the 10nm/7nm logic nodes. Intel already has encountered some difficulties, as the chip giant recently pushed out the volume ramp of its new 10nm process from the second half ... » read more

HPC Case Study: CFD Applications On ARM


In this paper, we examine the readiness and potential of ARM-based platforms for High Performance Computing, and have benchmarked two different computational fluid dynamics (CFD) applications. CFD represents one of the most widely used HPC applications in aerospace, automotive and other engineering areas such as turbine-design. For server hardware, we leverage the ThunderX platform from Cavium,... » read more

CAE Turns To HPC


How ANSYS is addressing the value of HPC technology within the CAE market, the main challenges to the use or uptake of HPC resources, and the future for HPC in CAE. The paper also briefly describes ANSYS Discovery Live — a new design tool that takes advantage of thousands of cores available in a GPU to produce instantaneous simulation results with every interactive change to the model. Discov... » read more

Power/Performance Bits: Dec. 5


Solar jet fuel Researchers at ETH Zurich demonstrated the ability to use solar energy to create the precursor to jet fuel from water and carbon dioxide, a process that could lead to carbon-neutral air travel. The scientists performed 295 consecutive cycles in a 4 kW solar reactor, yielding 700 standard liters of hydrogen and carbon monoxide (syngas), the precursor to kerosene and other liqu... » read more

Strategic Value Of High-Performance Computing For Research And Innovation


High-performance computing (HPC) is an enormous part of the present and future of engineering simulation. HPC enables engineers and researchers to gain high-fidelity insight into product behavior — insight that cannot be obtained without detailed simulation models. When applied to design exploration, HPC can lead to robust product performance and reduced warranty and maintenance costs. Wim Sl... » read more

Evaluating Speedcore IP For Your ASIC


By exploiting Achronix Speedcore embedded FPGA (eFPGA) IP — IP proven in multiple ASIC designs for wireless, datacenter and high-performance computing (HPC) applications — designers of SoCs can now add logic programmability to their solution, resulting in a single ASIC that can adapt to many applications. While many system architects may already have strong ideas on how an eFPGA core could ... » read more

Start Your HBM/2.5D Design Today


High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. In June 2015, AMD introduced its Fiji processor, the first HBM 2.5D design, which comp... » read more

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