tag: HLS

Customizing Processors
By Brian Bailey - 28 Jul, 2022 - Comments: 1

The design, verification, and implementation of a processor is the core competence of some companies, but others just want to whip up a small processor as quickly and cheaply as possible. What tools and options exist? Processors range from very small, simple cores that are deeply embedded into products to those operating at the highest possible clock speeds and throughputs in data centers. I... » read more

Heterogeneous Redundant Circuit Design Approaches for FPGAs
By Technical Paper Link - 12 Jul, 2022 - Comments: 0

New research paper titled "Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs" from researchers at Nagasaki University. Abstract (Partial) "In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach foc... » read more

Toward Democratized IC Design And Customized Computing
By Jason Cong - 28 Jun, 2022 - Comments: 0

Integrated circuit (IC) design is often considered a “black art,” restricted to only those with advanced degrees or years of training in electrical engineering. Given that the semiconductor industry is struggling to expand its workforce, IC design must be rendered more accessible. The benefit of customized computing General-purpose computers are widely used, but their performance improv... » read more

High-Level Synthesis: It’s Still Hardware Design
By Siemens EDA - 26 May, 2022 - Comments: 0

Hardware design using HLS is no different than the typical ASIC/FPGA design flow with the exception that C++/SystemC is being used along with HLS to create the RTL instead of hand coding it. The advantage of using HLS is that it speeds up RTL creation time and reduces verification time by producing bug free RTL quickly from a fully verified C++/SystemC source. The misconception that still exist... » read more

Structural Vs. Functional
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Formally Verifying SystemC/C++ Designs
By Rob van Blommestein - 29 Jul, 2021 - Comments: 0

We’re seeing an increase in the number of designs employing SystemC/C++. This isn’t surprising given the fact that specific use models have emerged to drive common design flows across engineering teams leading to the adoption of high-level synthesis (HLS) at many large semiconductor and electronic systems companies. These HLS tools are a popular method to rapidly generate design components ... » read more

Machine Learning At The Edge
By Siemens EDA - 12 May, 2021 - Comments: 0

Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet n... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Dec, 2020 - Comments: 0

Xilinx acquired the assets of Falcon Computing Solutions, a provider of high-level synthesis (HLS) compiler optimization technology for hardware acceleration of software applications. The acquisition will be integrated into the Xilinx Vitis Unified Software Platform to automate hardware-aware optimizations of C++ applications with minimal hardware expertise. “Our compiler provides a high degr... » read more

A Better Path From Simulink To RTL With Catapult HLS
By Mentor, a Siemens Business - 23 Nov, 2020 - Comments: 0

Design teams working on ASIC or FPGA projects often start with algorithm exploration using MATLAB in order to prove out the mathematical behavior of the functional blocks at a high level of abstraction. MATLAB as a high-level programming language doesn’t support hardware architecture modeling, so many teams use the Simulink environment for performing model-based, multi-domain simulation of th... » read more

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