tag: IEEE

Will The Chip Work?
By Ed Sperling - 26 Oct, 2015 - Comments: 0

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

Will The Chip Work?
By Ed Sperling - 19 Oct, 2015 - Comments: 1

IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

The Week In Review: Design/IoT
By Jesse Allen - 16 Oct, 2015 - Comments: 0

M&A Continuing to seek economies of scale in the IP industry, VeriSilicon and Vivante are combining forces. "This transaction creates an extensive semiconductor IP portfolio that will now include GPU cores, vision image processors, digital signal processors, video codecs, mixed signal IP and foundry foundation IP," said Wayne Dai, VeriSilicon chairman, president and CEO. The merged compa... » read more

Analog Meets Power In Standards Groups
By Ann Mutschler - 15 Oct, 2015 - Comments: 4

While the topic of language [getkc id="13" comment="Standards"] might be cringe-worthy for some, there is some noteworthy work underway in this area—particularly where power and analog meet paths. There are four main standards here: Verilog-A and Verilog-AMS VHDL-AMS SystemC-AMS SystemVerilog-AMS SystemVerilog-AMS is the newcomer, and while the standard won't be available for ... » read more

Power, Standards And The IoT
By Ed Sperling - 15 Oct, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power, standards and the IoT with Jerry Frenkil, director of open standards at [getentity id="22055" comment="Si2"]; Frank Schirrmeister, group director of product marketing of the System Development Suite at [getentity id="22032" e_name="Cadence"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"]; and Vojin Zivojno... » read more

Blog Review: Oct. 14
By Jesse Allen - 14 Oct, 2015 - Comments: 1

Rambus' Aharon Etengoff explores how new optical interfaces are aiding the burgeoning field of optogenetics, which combines genetic targeting of specific neurons or proteins with optical technology to study living neural circuits. Anand Shirahatti, Divyang Mali, and Naveen G of Synopsys team up to explain three features that make the MIPI UniPro mobile interconnect stand out, along with the ... » read more

The Week In Review: Design/IoT
By Jesse Allen - 31 Jul, 2015 - Comments: 0

M&A ARM acquired Israel-based Sansa Security, a provider of hardware security IP and software for advanced system-on-chip components deployed in IoT and mobile devices. The company's technology is currently deployed across a range of smart connected devices and enterprise systems. Sansa IP will be integrated into ARM's TrustZone and IoT portfolios. Standards Accellera sent UVM 1.2 ... » read more

Reliability After Planar Silicon
By Katherine Derbyshire - 29 Jul, 2015 - Comments: 2

Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

Can Copper Revolutionize Interconnects Again?
By Katherine Derbyshire - 10 Jun, 2015 - Comments: 2

Electromigration and resistivity present serious obstacles to interconnect scaling, as previously discussed. In a copper damascene process, grain growth is constrained by the narrow trenches into which copper is deposited. As the grain size approaches the mean free path of electrons in copper, electron scattering at sidewalls and grain boundaries increases and resistivity jumps. Meanwhile, incr... » read more

Week 50: It’s Not Just A Technical Conference, It’s An Ecosystem
By Anne Cirkel - 22 May, 2015 - Comments: 0

While our free “I love DAC” registration comes to an end this week, there are still a few weeks left to register for the full conference, the designer and IP track, or one of the many co-located events at DAC (see below). Over the last year I’ve been reminded often about the unique niche occupied by DAC. Just last week a good friend was trying to find an industry event in the greater EDA ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy