tag: imec

Week In Review: Manufacturing, Test
By Mark LaPedus - 17 Sep, 2021 - Comments: 0

Packaging and test Advantest and PDF Solutions have launched their first jointly developed offering since forming a partnership in 2020. The new product is called the Advantest Cloud Solutions Dynamic Parametric Test (ACS DPT) solution. It integrates PDF Solutions’ Exensio portfolio of data analytics with Advantest’s V93000 Parametric Test System. The ACS DPT solution is designed to op... » read more

Nudging 2D semiconductors forward
By Katherine Derbyshire - 16 Sep, 2021 - Comments: 1

The buzz about 2D materials replacing silicon appears to be premature. While 2D semiconductors have emerged as potential successors, it's not clear when or even if that will happen. As Iuliana Radu, Imec's director of quantum and exploratory computing observed, the “end” of silicon has been predicted many times before. It is not clear when 2D semiconductors will need to be ready. In fac... » read more

Challenges With Chiplets And Packaging
By Mark LaPedus - 15 Sep, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss IC packaging technology trends, chiplets, shortages and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Th... » read more

Will Monolithic 3D DRAM Happen?
By Bryon Moyer - 09 Sep, 2021 - Comments: 1

As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

How Chips Will Change Health Care
By Ed Sperling - 25 Aug, 2021 - Comments: 0

Jo De Boeck, chief strategy officer and executive vice president at imec, sat down with Semiconductor Engineering to talk about the intersection of medical and semiconductor technology, what's changing in how chips are being used, and what will happen in the short term and long-term. What follows are excerpts of that discussion. SE: Medical technology never advanced at the rate everybody... » read more

Manufacturing Bits: Aug. 24
By Mark LaPedus - 24 Aug, 2021 - Comments: 0

Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more

Inside Intel’s Ambitious Roadmap
By Mark LaPedus and Ed Sperling - 23 Aug, 2021 - Comments: 2

Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 20 Aug, 2021 - Comments: 0

Chipmakers, OEMs At Intel’s Architecture Day this week, the company revealed several new chip architectures. Some were already announced, while others are new. These include Intel’s first performance hybrid architecture, a data center architecture, a discrete gaming graphics processing unit (GPU) architecture, infrastructure processing units (IPUs), and a data center GPU architecture. Here... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Aug, 2021 - Comments: 0

Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

Angstrom-Level Measurements With AFMs
By Mark LaPedus - 19 Aug, 2021 - Comments: 0

Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

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