tag: imec

Managing Thermal-Induced Stress In Chips
By Karen Heyman - 16 Feb, 2023 - Comments: 0

At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Devices And Transistors For The Next 75 Years
By Laura Peters - 16 Feb, 2023 - Comments: 0

The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bon... » read more

Disaggregating And Extending Operating Systems
By Karen Heyman - 09 Feb, 2023 - Comments: 0

The push toward disaggregation and customization in hardware is starting to be mirrored on the software side, where operating systems are becoming smaller and more targeted, supplemented with additional software that can be optimized for different functions. There are two main causes for this shift. The first is rising demand for highly optimized and increasingly heterogeneous designs, which... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics
By Ed Sperling - 08 Feb, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Bump Reliability is Challenged By Latent Defects
By Karen Heyman - 07 Feb, 2023 - Comments: 0

Thermal stress is a well-known problem in advanced packaging, along with the challenges of mechanical stress. Both are exacerbated by heterogenous integration, which often requires mingling materials with incompatible coefficients of thermal expansion (CTE). Effects are already showing up and will likely only get worse as package densities increase beyond 1,000 bumps per chip. “You comb... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 03 Feb, 2023 - Comments: 0

Imec released its semiconductor roadmap, which calls for doubling compute power every six months to handle the data explosion and new data-intensive problems. Imec named five walls (scaling, memory, power, sustainability, cost) that need to be dismantled. The roadmap (below) stretches from 7nm to 0.2nm (2 angstroms) by 2036, and includes four generations of gate-all-around FETs followed by thre... » read more

Collaboration Widens Among Big Chip Companies
By Ed Sperling - 23 Jan, 2023 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the growing need for collaboration among equipment and tools vendors, the impact of systems companies and increases in complexity, and how to handle a push for more customization while controlling costs, with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computati... » read more

Supply Chain Collaboration Key To Making Chip Industry More Sustainable
By Cassandra Melvin - 19 Jan, 2023 - Comments: 0

Coming in the wake of the COP27, the Smart and Green Manufacturing Summit at SEMICON Europa 2022 (Munich, 15-17 November) had a timely focus on the semiconductor industry’s contribution to meeting the United Nations’ target of limiting global warming to 1.5°C above pre-industrial levels. However, in an industry as large and valuable as semiconductors, social as well as environmental imp... » read more

How Far Will Copper Interconnects Scale?
By Laura Peters - 15 Dec, 2022 - Comments: 0

As leading chipmakers continue to scale finFETs — and soon nanosheet transistors — to ever-tighter pitches, the smallest metal lines eventually will become untenable using copper with its liner and barrier metals. What comes next, and when, is still to be determined. There are multiple options being explored, each with its own set of tradeoffs. Ever since IBM introduced the industry to c... » read more

Ferroelectrics: The Dream Of Negative Capacitance
By Katherine Derbyshire - 15 Dec, 2022 - Comments: 0

Ferroelectrics are getting a serious re-examination, as chipmakers look for new options to maintain drive current. Ferroelectric materials can provide non-volatile memory, serving an important functional gap somewhere between DRAM and flash memory. Indeed, ferroelectrics for memory and 2D channels for transistors were two highlights of the recent IEEE Electron Device Meeting. Ferroelectri... » read more

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