tag: imec

Power/Performance Bits: Sept. 24
By Jesse Allen - 24 Sep, 2019 - Comments: 0

Textiles for energy storage Scientists at RMIT University developed a way to laser print waterproof textiles with graphene supercapacitors for embedded energy storage. The process takes three minutes to create a 10x10cm patch. The electronic textile is based on nylon coated with PDMS on one side for waterproofing. The other side was paint coated with graphene oxide and a binder to form thin... » read more

The Race To Next-Gen 2.5D/3D Packages
By Mark LaPedus - 23 Sep, 2019 - Comments: 4

Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

The Next New Memories
By Mark LaPedus - 15 Aug, 2019 - Comments: 2

Several next-generation memory types are ramping up after years of R&D, but there are still more new memories in the research pipeline. Today, several next-generation memories, such as MRAM, phase-change memory (PCM) and ReRAM, are shipping to one degree or another. Some of the next new memories are extensions of these technologies. Others are based on entirely new technologies or involve ar... » read more

Creating 2D Compounds
By Katherine Derbyshire - 18 Jul, 2019 - Comments: 1

A 2D material, by definition, has no surface dangling bonds. A bulk material with plate-like structure, such as graphite, is composed of thin layers with a weakly bonded cleavage plane between. What this means is a monolayer of graphite will seek to satisfy its exposed dangling bonds by absorbing other materials. A monolayer of graphene, in contrast, is energetically complete without a secon... » read more

Manufacturing Bits: July 10
By Mark LaPedus - 10 Jul, 2019 - Comments: 0

Semicon West It’s Semicon West time again. Here’s the first wave of announcements at the event: Applied Materials has unveiled a pair of tools aimed at accelerating the industry adoption for new memories. First, Applied rolled out the Endura Clover MRAM PVD system. The system is an integrated platform for MRAM devices. Second, the company introduced the Endura Impulse PVD platform for P... » read more

EUV, Deep Learning Issues In Mask Making
By Mark LaPedus - 01 Jul, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss extreme ultraviolet (EUV) lithography, photomask technologies and machine learning issues with Emily Gallagher, principal member of the technical staff at Imec; Harry Levinson, principal at HJL Lithography; Chris Spence, vice president of advanced technology development at ASML; Banqiu Wu, senior director of process development at Applied Materials;... » read more

Manufacturing Bits: June 25
By Mark LaPedus - 25 Jun, 2019 - Comments: 0

Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

System Bits: June 25
By Jeff Dorsch - 25 Jun, 2019 - Comments: 0

Supercomputers around the world At last week’s International Supercomputing Conference in Frankfurt, Germany, the 53rd biannual list of the Top500 of the most powerful computing systems in the world was released. Broken out by countries of installation, China has 219 of the world’s 500 fastest supercomputers, compared with 116 in the United States. Ranking by percent of list flops, the ... » read more

5nm Vs. 3nm
By Mark LaPedus - 24 Jun, 2019 - Comments: 16

Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

Partitioning In 3D
By Katherine Derbyshire - 23 May, 2019 - Comments: 2

The best way to improve transistor density isn't necessarily to cram more of them onto a single die. Moore’s Law in its original form stated that device density doubles about every two years while cost remains constant. It relied on the observation that the cost of a processed silicon wafer remained constant regardless of the number of devices printed on it, which in turn depended on litho... » read more

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