Manufacturing Bits: July 21

Intel’s next-gen MRAM; silicon oxide ReRAM; FeFETs.


Intel’s next-gen MRAM
At the recent 2020 Symposia on VLSI Technology and Circuits, Intel presented a paper on a CMOS-compatible spin-orbit torque MRAM (SOT-MRAM) device.

Still in R&D, SOT-MRAM is a next-generation MRAM designed to replace SRAM. Generally, processors integrate a CPU, SRAM and a variety of other functions. SRAM stores instructions that are rapidly needed by the processor. This is called Level 1 cache memory.

SRAM-based L1 cache is fast, but it also occupies too much space on the chip. So for years, the industry has been looking to replace SRAM, namely with today’s spin-transfer torque MRAM (STT-MRAM). STT-MRAM features the speed of SRAM and the non-volatility of flash with unlimited endurance.

In production today, STT-MRAM is a one-transistor architecture with a magnetic tunnel junction (MTJ) memory cell. It uses the magnetism of electron spin to provide non-volatile properties in chips. The write and read functions share the same parallel path in the MTJ cell.

The problem? STT-MRAM isn’t fast enough to replace SRAM for L1 and/or L2 cache. There are some reliability issues as well.

That’s why the industry is exploring SOT-MRAM as a replacement for SRAM. SOT-MRAM resembles STT-MRAM. The difference is that SOT-MRAM integrates an SOT layer under the device. It induces switching of the layer by injecting an in-plane current in an adjacent SOT layer, according to Imec.

Today, though, the biggest problem with SOT-MRAM is that it only switches about 50% of the time. To address the challenges, several entities are working on the technology, including Imec, Intel and others. “Replacing high-density SRAM with SOT-MRAM is expected to provide a 2-3X density leap,” said Noriyuki Sato, a researcher at Intel, in a paper at the 2020 Symposia on VLSI Technology and Circuits. Others contributed to the work.

For its part, Intel has demonstrated a CMOS-compatible process of an SOT-MRAM device with a bilayer SOT bottom electrode. “We experimentally validated the two-pulse field-free SOT switching scheme with spin-transfer torque assist at 10ns. Unlike conventional field-free SOT switching schemes, the demonstrated scheme adds no complexity to process integration,” Sato said. “An effective spin-Hall angle of 0.27, a median tunneling magneto-resistance ratio of 127% at electrical CD of 57nm, and a 96% resistance-based MTJ yield on 300mm scale were achieved.”

To develop the technology, Intel developed a new SOT bottom electrode (BE) structure. This consists of two heavy-metal layers and an MTJ etch process that has a high selectivity between them. “This allows us to precisely control the over-etch thickness into the SOT BE across a 300 mm wafer,” Sato said.

Silicon oxide ReRAM
At the VLSI Technology and Circuits event, Politecnico di Milano, Weebit Nano and Leti presented a joint research paper on a novel artificial intelligence (AI) self-learning demonstration based on ReRAM.

The technology is based on Weebit’s silicon oxide (SiOx) ReRAM, which solves a major problem. Artificial neural networks (ANNs) can outperform humans in terms of object recognition, but the technology cannot acquire new information without forgetting trained tasks, according to researchers.

In response, researchers developed SiOx RRAM-based inference hardware. The technology is capable of merging the efficiency of convolutional ANNs and the plasticity of spiking networks. In other words, researchers devised a brain-inspired AI system, which can perform unsupervised learning tasks with high accuracy results.

The technology enables the hardware to learn new things without forgetting the trained tasks of previously acquired information. Researchers validated the accuracy of the system with MNIST (99.3%), noisy N-MNIST (96%), Fashion-MNIST (93%) and CIFAR-10 (91%) datasets.

Researchers demonstrated that the circuit plastically adapts its operative frequency for power saving and enables continual learning of up to 50% of non-trained classes. This optimizes the classification and enables the re-training of the filters, thus overcoming the catastrophic forgetting of standard ANNs.

Daniele Ielmini, a professor at Politecnico di Milano, said: “Continual learning is essential for us as humans to accumulate knowledge. Artificial neural networks currently lack this ability, as the previous knowledge is generally erased by a second training – a process known as catastrophic forgetting. This AI system combines the best of both worlds, namely the accuracy of deep learning and the flexibility of the human brain, thus moving one step closer to the realization of brain-like hardware.”

Coby Hanoch, CEO of Weebit Nano, said: “Weebit’s progress with Professor Ielmini on a joint neuromorphic ReRAM project over the past year, demonstrates the capability of our silicon oxide ReRAM technology in artificial intelligence applications. Our ongoing collaboration will ensure our technology is at the forefront of future artificial intelligence and neuromorphic computing applications, addressing the challenges of tomorrow.”

Besides SOT-MRAM and ReRAM, the industry is also working on another new memory type called the ferroelectric FET (FeFET).

Still in R&D, a FeFET makes use of an existing logic transistor with a high-k/metal-gate stack based on hafnium oxide. The gate insulator is then modified with ferroelectric properties.

The industry is developing embedded and standalone FeFET devices. An embedded FeFET would be integrated in a controller. A standalone device may become a new memory type or a DRAM replacement.

“FeFET memory based on ferroelectric (FE) HfO2 with a thin interfacial layer (IL) is a compelling candidate for storage-class memory and neuromorphic computing,” said Yung-Hsien Wu from Taiwan’s National Tsing Hua University, in a paper at the 2020 Symposia on VLSI Technology and Circuits. Others contributed to the work. “A large memory window (MW) along with robust endurance is desirable for FeFET memory. However, most FeFET memory devices display a limited MW ranging from 0.7-1.5 V and degraded endurance, which may pose challenges for further applications.”

In the paper, National Tsing Hua University demonstrated a FeFET memory featuring a large memory window and robust endurance. Researchers used a high-k AlON material to boost the performance.

“Without destabilizing the ferroelectric (FE) phase, high-k AlON with N of ~13% was proposed as the interfacial layer (IL) between FE HfZrOx (HZO) and Si substrate for FeFET memory to enhance the memory window (MW) while improving reliability compared to SiO2 IL,” Wu said. “The AlON-based memory shows promising performance in terms of a large MW of 3.1 V by ±4 V operation, long retention up to 10 years, and robust endurance up to 105 cycles with a long pulse width of 10-4 s.”

The AlON and FE-HZO can be integrated in a single ALD step to simplify the process. AlON paves a promising path to enable more reliable and feasible FeFET memory.


Johnson says:

What could be more done to make memory and processors cheaper while still maintaining reliability, and how about it’s lifespan, we don’t want those memory chips & processors to fail within 10 years or so, so am not a big fan of these R&D as we may will get smartphones wich will only have a lifespan iof 2 years,,
Also how about a biochip wich uses bacterias instead of switches, not only will there be minor dying rutless inside because of dying bacterias soon or later, but that biochip may not always work because of bacterias responding randomly from the pulses,some will respond faster then other ones while other ones refuse to respond, so you can imagine how apps could randomly crash or glitching out because of this,
So i say no against all off these stuff as of now.

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