tag: imec

Improving Patterning Yield At The 5nm Semiconductor Node
By Benjamin Vincent - 29 Mar, 2018 - Comments: 0

Engineering decisions are always data-driven. As scientists, we only believe in facts and not in intuition or feelings. At the manufacturing stage, the semiconductor industry is eager to provide data and facts to engineers based upon metrics such as the quantity of wafers produced per hour and sites/devices tested on each of those wafers. The massive quantity of data generated in semiconduct... » read more

EUV’s New Problem Areas
By Mark LaPedus - 19 Mar, 2018 - Comments: 2

Extreme ultraviolet (EUV) lithography is moving closer to production, but problematic variations—also known as stochastic effects—are resurfacing and creating more challenges for the long-overdue technology. GlobalFoundries, Intel, Samsung and TSMC hope to insert [gettech id="31045" comment="EUV"] lithography into production at 7nm and/or 5nm. But as before, EUV consists of several compo... » read more

DSA Re-Enters Litho Picture
By Mark LaPedus - 15 Mar, 2018 - Comments: 1

By Mark LaPedus and Ed Sperling Directed self-assembly (DSA) is moving back onto the patterning radar screen amid ongoing challenges in lithography. Intel continues to have a keen interest in [gettech id="31046" t_name="DSA"], while other chipmakers are taking another hard look at the technology, according to multiple industry sources. DSA isn't like a traditional [getkc id="80" kc_name="... » read more

More Lithography/Mask Challenges (part 1)
By Mark LaPedus - 15 Mar, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

Why All Nodes Won’t Work
By Ed Sperling - 08 Mar, 2018 - Comments: 4

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 02 Mar, 2018 - Comments: 0

Fab tools Samsung Electronics has broken ground on a new extreme ultraviolet (EUV) lithography facility in Hwaseong, South Korea. The new EUV facility is expected to be completed within the second half of 2019 with production slated for 2020. The initial investment in the new EUV line is projected to reach $6 billion by 2020. Imec and Cadence Design Systems have collaborated on the develop... » read more

The Week In Review: Design
By Jesse Allen - 02 Mar, 2018 - Comments: 0

Startup OnScale launched with advanced CAE multi-physics solvers that are seamlessly integrated with a scalable, high performance cloud computing platform built on Amazon's AWS. The company's model is built around a Solver-as-a-Service pay-as-you-go subscription model and targets 5G, IoT/Industrial IoT, biomedical, and autonomous car markets. The company has $3 million in strategic seed fund... » read more

What’s Next In Neuromorphic Computing
By Katherine Derbyshire - 15 Feb, 2018 - Comments: 2

To integrate devices into functioning systems, it's necessary to consider what those systems are actually supposed to do. Regardless of the application, [getkc id="305" kc_name="machine learning"] tasks involve a training phase and an inference phase. In the training phase, the system is presented with a large dataset and learns how to "correctly" analyze it. In supervised learning, the data... » read more

Transistor Options Beyond 3nm
By Mark LaPedus - 15 Feb, 2018 - Comments: 18

Despite a slowdown in chip scaling amid soaring costs, the industry continues to search for a new transistor type 5 to 10 years out—particularly for the 2nm and 1nm nodes. Specifically, the industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, accord... » read more

EUV Reticle Print Verification With Advanced Broadband Optical Wafer Inspection And e-Beam Review Systems
By KLA - 14 Feb, 2018 - Comments: 0

As the Extreme Ultraviolet (EUV) lithography ecosystem is being actively mapped out to enable sub-7nm design rule devices, there is an immediate and imperative need to identify the EUV reticle (mask) inspection methodologies. The introduction of additional particle sources due to the vacuum system and potential growth of haze defects or other film or particle depositions on the reticle, in comb... » read more

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