tag: imec

The Future Of Patterning
By Jan Willis - 18 May, 2017 - Comments: 0

Greg McIntyre, director of advanced patterning at imec, offers his thoughts on what it’s like to work at one of the world’s leading nanoelectronics R&D centers, as well as the importance of eBeam technology to lithography and mask making, what’s driving up confidence in EUV, and the latest on imec’s joint venture with JSR in EUV resist development. [youtube vid=q8cA_9rWecU] » read more

Manufacturing Bits: May 16
By Mark LaPedus - 16 May, 2017 - Comments: 0

Musical learning chips Imec has demonstrated a neuromorphic chip. The brain-inspired chip, based on OxRAM technology, has the capability of self-learning and has been demonstrated to have the ability to compose music. Imec has combined state-of-the-art hardware and software to design chips that feature these characteristics of a self-learning system. Imec’s goal is to design the process t... » read more

Inside Lithography And Masks
By Mark LaPedus - 01 May, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="IMEC"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cov... » read more

Will Self-Heating Stop FinFETs
By Katherine Derbyshire - 20 Apr, 2017 - Comments: 0

New transistor designs and new materials don’t appear out of thin air. Their adoption always is driven by the limitations of the incumbent technology. Silicon germanium and other compound semiconductors are interesting because they promise superior carrier mobility relative to silicon. [getkc id="185" kc_name="FinFET"] transistor designs help minimize short channel effects, a critical limi... » read more

System Bits: April 18
By Ann Mutschler - 18 Apr, 2017 - Comments: 0

RISC-V errors Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retr... » read more

Inside Lithography And Masks
By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 31 Mar, 2017 - Comments: 0

Chipmakers At an event, Intel’s Technology and Manufacturing group outlined the company's vision. As part of the event, Intel reiterated what many are saying—the current node designations are meaningless and misleading. “For example, Intel estimates that its 14nm solution that has been out in the market since 2014 should be equal to 10nm solutions released by competitors in the near futu... » read more

The Week In Review: Design
By Jesse Allen - 24 Mar, 2017 - Comments: 0

Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

Patterning Problems Pile Up
By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

TFETs Cut Sub-Threshold Swing
By Katherine Derbyshire - 16 Mar, 2017 - Comments: 0

One of the main obstacles to continued transistor scaling is power consumption. As gate length decreases, the sub-threshold swing (SS) — the gate voltage required to change the drain current by one order of magnitude — increases. As Qin Zhang, Wei Zhao, and Alan Seabaugh of Notre Dame explained in 2006, SS faces a theoretical minimum of 60 mV/decade at room temperature in conventional MO... » read more

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