Challenges Mount For Interconnect


By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

New Terms, New Problems


At the distant forefront of research there is very little marketing. After all, what’s the point? Until recently, much of this stuff was theoretical physics, and products weren’t even a consideration. It wasn’t until the past decade when we could actually see atoms. We had to theorize them. And it wasn’t until the past few years when we actually began taking stacked die seriously. Bu... » read more

RF, MEMS, Photonics Driving 3D Stacking


By Pallab Chatterjee At Semicon West, a number of the key speakers and TechXPOTs were talking about current products being assembled and shipped with 3D technology. 3D die stacking is no longer a technology of the future. In fact it has been here for many years and has been used in millions, if not billions, of consumer, commercial and high-reliability designs. The two leading technologies ... » read more

Building A Better CMOS FET


By Barry Pangrle SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice overview presentation on FinFETs. From a power and performance standpoint, we’ve seen some early pre-production information released from Intel that I briefly discussed here. Serge�... » read more

Healthy Living Electronics Dominated By Power


By Pallab Chatterjee The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products. The common theme between all the talks is that health-care is being driven by mobility, information flow, a... » read more

The Shape Of Things To Come


By David Lammers Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations. “This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech... » read more

Stressing Over 3D


By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

3D Integration: Extending Moore’s Law Into The Next Decade


By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

Handcrafted Designs


Ludo Deferm, VP of business development at IMEC, the Belgian research house, talks about changes ahead at future process nodes. [youtube vid=8b6O52qY0bs] » read more

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