Patterning Interconnects At 10nm And Below

By Applied Materials - 20 Aug, 2015 - Comments: 0

By Connie Duncan Chip manufacturers today build billions of transistors on a chip, delivering incredible computing power to consumers. What often gets overlooked is how hard it’s getting to create the many miles of ultra-thin copper wiring used to connect each of the transistors. Patterning these electrical pathways is becoming increasingly challenging as they grow denser and finer, and any ... » read more

Let’s Talk Open Source

By Ernest Worthman - 06 Jul, 2015 - Comments: 0

Of late I have been hearing some rumblings about open source for the IoE. The sad part is that there is still talk about anything else. Even though the IoE remains a dream to many, the shrewd marketers already are scheming on how to make their product the one that leads that pack, and many see proprietary source code as a way to differentiate themselves. I can see that in any number of appli... » read more

Can Copper Revolutionize Interconnects Again?

By Katherine Derbyshire - 10 Jun, 2015 - Comments: 2

Electromigration and resistivity present serious obstacles to interconnect scaling, as previously discussed. In a copper damascene process, grain growth is constrained by the narrow trenches into which copper is deposited. As the grain size approaches the mean free path of electrons in copper, electron scattering at sidewalls and grain boundaries increases and resistivity jumps. Meanwhile, incr... » read more

10nm Fab Challenges

By Mark LaPedus - 21 May, 2015 - Comments: 1

After a promising start in 2015, the semiconductor equipment industry is currently experiencing a slight lull. The pause is expected to be short-lived, however. Suppliers of [getkc id="208" comment="3D NAND"] devices are expected to add more fab capacity later this year. And about the same time, foundries are expected to order the first wave of high-volume production tools for 10nm. At 10nm... » read more

Waiting For Next-Gen Metrology

By Mark LaPedus - 21 May, 2015 - Comments: 0

Chipmakers continue to march down the various process nodes, but the industry will require new breakthroughs to extend IC scaling at 10nm and beyond. In fact, the industry will require innovations in at least two main areas—patterning and the [getkc id="36" comment="Interconnect"]. There are other areas of concern, but one technology is quickly rising near the top of the list—metrology.... » read more

Streamlining Interconnect Integration Accelerates Globally Distributed Design

By Kurt Shuler - 26 Feb, 2015 - Comments: 0

As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on a particular aspect of the SoC, the hard part comes in integrating these individual design efforts together. When something goes wrong and it doesn’t work, the compan... » read more

Signal Integrity Issues

By Ed Sperling - 15 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

Designing the Right Architecture

By Synopsys - 14 Jan, 2015 - Comments: 0

Designing the right architecture of a multi-processor SoC for today's sophisticated electronic products is a challenging task. The most critical element for meeting the performance requirements of the entire system is the interconnect and memory architecture. These SoC infrastructure IP components are highly configurable and need to be customized to the communication needs of all the other modu... » read more

The Internet Of Cores

By Brian Bailey - 20 Nov, 2014 - Comments: 0

Ever since the birth of the third-party [getkc id="43" comment="IP"] market, there has been a desire for plug-and-play compatibility between cores. Part of the value proposition of reuse is that a block has been used before, and has been verified and validated by having been implemented in silicon. By re-using the core, many of these tasks no longer land on the [getkc id="81" kc_name="SoC"] dev... » read more

Why Investments At Advanced Nodes Matter

By Ed Sperling - 18 Sep, 2014 - Comments: 0

Despite all the talk about rising costs of development, uncertainties about lithography and talk about the death of Moore’s Law, a record number of companies are developing chips at 16nm/14nm. That may sound surprising, but asking why that’s happening is probably the wrong question. The really critical question is what they’re going to do with those chips. What’s become quite evident... » read more

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tag: interconnects