The Week In Review: Design

Arm’s AI push; SerDes validation; formal tool certification; Gen-Z.


Tools & IP
Arm unveiled a new suite of IP focused on machine learning for edge devices. Currently dubbed Project Trillium, it includes the Arm ML processor, the second-generation Arm Object Detection (OD) processor, and open-source Arm NN software. The ML processor provides more than 4.6 TOPs in mobile environments with efficiency of 3 TOPs/W. People detection is a focus of the OD processor, including metadata on human activity and object identification from 50×60 pixels at 60fps. The NN SDK performs translation of existing neural network frameworks, allowing them to run across Arm Cortex CPUs and Arm Mali GPUs.

Mentor added an end-to-end fully automated SerDes channel validation solution to its HyperLynx PCB simulation product. The update adds tool-embedded protocol-specific channel compliance and includes a 3D explorer feature for design and layout optimization of non-uniform structures like breakouts and vias.

OneSpin’s tool development and testing process has been audited by TÜV SÜD, allowing the company to provide certified formal verification solutions meeting tool qualification requirements set by functional safety standards ISO 26262, IEC 61508 and EN 50128/SIL 3. OneSpin plans a series of Tool Qualification Kits to speed up the process of tool qualification for users, beginning with one for EC-FPGA, an automatic sequential equivalence checker that prevents FPGA design flows from introducing synthesis, place-and-route and other implementation errors.

Ansys debuted Discovery Live for instant 3D simulation. Coupled with direct geometry modeling, the tool aims to enable interactive design exploration. Capabilities include thermal, structural, and fluid analysis.

MIPS and NetSpeed teamed up to integrate MIPS Warrior I-Class I6500 processors with NetSpeed’s Gemini network-on-chip IP. NetSpeed will be the preferred interconnect partner for MIPS, providing coherency between multiple MIPS processor clusters and the rest of the SoC. The collaboration targets AI and machine learning applications, particularly in automotive.

Arbe Robotics licensed Arteris IP’s FlexNoC interconnect IP for use in its 4D High-resolution Automotive Radar chipset. Arbe Robotics cited on-chip bandwidth and latency requirements associated with real-time detection of obstacles at a range of 300 meters with a wide field of view at ultra-high resolution.

Gemalto signed a patent license agreement with Rambus, giving the company access to patents covering Differential Power Analysis (DPA) Countermeasures, which protect devices and integrated circuits against DPA and other related side-channel attacks.

The Gen-Z Consortium released its Gen-Z Core Specification 1.0. The Gen-Z technology focuses on an open systems interconnect designed to provide memory semantic access to data and devices via direct-attached, switched or fabric topologies.

Cavium used the Gen-Z interconnect in its ThunderX2 ARM server, and IntelliProp will release a full package of Gen-Z IP Cores, including Requester/Responder for both FPGA and ASICs. Avery Design Systems plans to provide VIP for the specification.

FPGA 2018: Feb. 25-27 in Monterey, CA. The conference includes a workshop on packet processing with the P4 language, a panel and several presentations focused on machine learning, and a look at new architectures.

DVCon 2018: Feb. 26-Mar. 1 in San Jose, CA. Features include tutorials on the Portable Stimulus Standard and UVM, a keynote on how new segments in the industry are changing verification, and a new slate of short workshops. Brian Bailey takes a look at what to check out.

Embedded World 2018: Feb. 27-Mar. 1 in Nuremberg, Germany. The trade show and conference focused on embedded systems will feature keynotes on  embedded systems incorporating artificial intelligence, displays, and OLEDs.

ASICs Unlock Deep Learning Innovation: Mar. 14, 3:30 p.m. – 7:30 p.m., in Mountain View, CA. This seminar will explore an implementation platform for deep learning ASICs including HBM2 and 2.5D system-in-package design and implementation. The event is hosted by Samsung Electronics, Amkor, eSilicon, and Northwest Logic with a keynote by Ty Garibay, CTO of Arteris IP.

ISQED 2018: Mar. 13-14 in Santa Clara, CA. The conference highlights design techniques and methods, design processes, and EDA design methodologies and tools to improve the quality and manufacturability of ICs. Keynote speakers will address asymmetry in electronics, opportunities in AI, and recent materials and design innovations. Tutorials focus on power-aware test, power for IoT, and cyber-physical systems.

DAC 2018: June 24-28 in San Francisco, CA. DAC is adding a new Late-Breaking Results submission category, providing an opportunity to announce new findings that were not available during the regular paper submission process. The submission deadline is March 1.

Leave a Reply

(Note: This name will be displayed publicly)