What’s So Different About Interposer Signal Integrity?

By Kelly Damalou - 28 Oct, 2022 - Comments: 0

By Kelly Damalou and Pete Gasperini To achieve gains in power, performance, area, and cost, 3D-IC architectures are pushing electronics design to new limits. Silicon integration technology and associated devices have undergone an impressive evolution over the last several decades. Their development encourages technological advancement in applications like high-performance computing, Artificial... » read more

Which Foundry Is In The Lead? It Depends.

By Ed Sperling - 26 Oct, 2022 - Comments: 2

The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed. This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google... » read more

Holistic 3D-IC Interposer Analysis In Product Designs

By Ben Gu - 22 Sep, 2022 - Comments: 1

The miniaturization trend in electronic devices and the rise in smart and IoT device segments make adopting heterogeneous integration of chip components or 3D-ICs a viable option for miniaturization and better interconnection. This vertical stacking of ICs enables the next generation of sophisticated, intelligent devices, necessitating high chip density and terabytes of bandwidth. As per the f... » read more

Keeping IC Packages Cool

By Laura Peters and Karen Heyman - 07 Jun, 2022 - Comments: 0

Placing multiple chips into a package side-by-side can alleviate thermal issues, but as companies dive further into die stacking and denser packaging to boost performance and reduce power, they are wrestling with a whole new set of heat-related issues. The shift to advanced packaging enables chipmakers to meet demands for increasing bandwidth, clock speeds, and power density for high perform... » read more

Chiplets: Current Status

By Andy Heinig - 12 May, 2022 - Comments: 0

Recent weeks have seen a number of interesting developments in the area of chiplets. An increasing number of products based on chiplets have been brought to market, especially in the processors segment. For example, Apple and AMD now have processors with chiplets on the market and under production in high volumes. On one hand, this means that sufficient production capacity has now been built up... » read more

Preparing For 3D-ICs

By Ed Sperling - 16 Feb, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Design Challenges Increasing For Mixed-Die Packages

By Ann Mutschler - 09 Feb, 2022 - Comments: 0

The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore's Law, making heterogeneous combinations of die easier, cheaper, and more predictable. There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to th... » read more

Next-Gen 3D Chip/Packaging Race Begins

By Mark LaPedus - 31 Jan, 2022 - Comments: 5

The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages. AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips usin... » read more

Expanding Advanced Packaging Production In The U.S.

By Mark LaPedus - 05 Jan, 2022 - Comments: 0

The United States is taking the first steps toward bringing larger-scale IC packaging production capabilities back to the U.S. as supply chain concerns and trade tensions grow. The U.S. is among the leaders in developing packages, especially new and advanced forms of the technology that promise to shake up the semiconductor landscape. And while the U.S. has several packaging vendors, North A... » read more

Challenges With Stacking Memory On Logic

By Ed Sperling - 22 Dec, 2021 - Comments: 1

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tag: interposers

What’s So Different About Interposer Signal Integrity?

Which Foundry Is In The Lead? It Depends.

Holistic 3D-IC Interposer Analysis In Product Designs

Keeping IC Packages Cool

Chiplets: Current Status

Preparing For 3D-ICs

Design Challenges Increasing For Mixed-Die Packages

Next-Gen 3D Chip/Packaging Race Begins

Expanding Advanced Packaging Production In The U.S.

Challenges With Stacking Memory On Logic

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