DAC 2015: Day 3


The schedule for today revolves around eating and it is perfectly balanced between the big three. The morning starts with breakfast for the Cadence panel titled "Crossing the Great Divide: How to Safely Navigate the move from 28nm to 16FF+." The panel was moderated by Brian Fuller and panelists included Jayanta Lahiri from ARM, Afshin Montaz from Broadcom, Scott McCormack from Freescale, Yan... » read more

DAC 2015: Day One


It requires a certain dedication to attend technical DAC sessions on a Sunday morning, but full day workshops start before 9:00am for those dedicated to hearing about the latest work being conducted in academia and the research arm of industry. These are highly technical sessions that target academics and those serious about keeping a pulse on up and coming technologies. One such workshop wa... » read more

Executive Insight: Charles Janac


SE: One of the big stories these days is consolidation. What are you seeing on your side? Janac: There are about 230 companies doing SoCs right now. Maybe 150 should be doing that. As the game gets more expensive and more difficult, some of the companies that don't have volume may have to do something else. Consolidation is part of that. But you're also going to see movement toward platforms... » read more

IP Market Shifts Direction


Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

What’s Different At 16/14nm?


Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

Design Virtualization And Its Impact On SoC Design


At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC. Using conventional design methodologies, it is very difficult to know if the correct options have been chosen. There is simply ... » read more

Week 50: It’s Not Just A Technical Conference, It’s An Ecosystem


While our free “I love DAC” registration comes to an end this week, there are still a few weeks left to register for the full conference, the designer and IP track, or one of the many co-located events at DAC (see below). Over the last year I’ve been reminded often about the unique niche occupied by DAC. Just last week a good friend was trying to find an industry event in the greater EDA ... » read more

IP Market Shifts Direction


Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

Problems Ahead for EDA


Semiconductor Engineering sat down with [getperson id="11411" comment="Bill Neifert"], chief technology officer at [getentity id="22521" comment="Carbon Design Systems"]; [getperson id="11032" comment="Simon Davidmann”], chief executive officer for [getentity id="22036" e_name="Imperas”]; Randy Smith, vice president of marketing for [getentity id="22605" e_name="Sonics"] and Michel Courtoy,... » read more

Trouble Ahead For IP industry?


[getkc id="106" kc_name="Power-aware design"] has risen from an afterthought to a primary design constraint for some design types. Initially it was smart phones and other battery operated devices. It has consistently expanded into additional areas including those plugged into the wall and those plugged into the grid. Some parts of the world are imposing restrictions on the power that a device c... » read more

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