Challenges Increase for IP At Advanced Nodes

By Ann Mutschler - 25 Sep, 2014 - Comments: 1

At advanced process nodes such as 16/14/10nm, designing [getkc id="43" comment="IP"] is a much tougher nut to crack due to complexity and other considerations, not to mention then trying to migrate and/or re-use that IP. Still, engineering teams are looking for leverage wherever they can find it in their designs amid the technical challenges to overcome. Tomasz Wojcicki, vice president of c... » read more

Evaluation Platforms Key To Complex IP Integration

By Swamy Irrinki - 25 Sep, 2014 - Comments: 0

Just because a chip is complex to build doesn’t mean it has to take a long time. Runaway complexity in SoC and ASIC design is forcing chip companies to consider different methodologies and approaches that could actually simplify and speed up the whole process. The first step in this process was commercial IP, and its growing popularity attests to the fact that chipmakers are looking for... » read more

Time To Market Concerns Worsen

By Ed Sperling - 25 Sep, 2014 - Comments: 1

Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern. Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over th... » read more

Quantifying IP Entitlement For 14/16nm Technologies

By eSilicon - 24 Sep, 2014 - Comments: 0

The scaling benefits of [getkc id="74" comment="Moore"s Law"] are being seriously tested at 28nm. It is no longer a given that the cost per gate will go down at leading edge process nodes below 28nm, e.g., 20nm though 14nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex [getkc id="81" comment="SoC"] (So... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores

By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

The Week In Review: Design

By Ed Sperling - 19 Sep, 2014 - Comments: 0

Tools Open-Silicon uncorked a 28Gbps SerDes evaluation platform, complete with board, test chip and characterization data, which it says will speed up and simplify development of chips for 100G networks. The chip utilizes PHY IP from Semtech. IP Synopsys rolled out MIPI C-PHY verification IP that utilizes a three-phase coding technique for faster camera, display and SoC interfaces. http://... » read more

Changing The IP Supplier Paradigm

By Brian Bailey - 17 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down with Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research; John Koeter, vice president of marketing for the Solutions Group at [getentity id="22035" e_name="Synopsys"]; Mike Gianfagna, vice president of marketing for [getentity id="22242" e_name="eSilicon"]; Peter McGuinness, director of technology marketing at [getentity id="22709" e_nam... » read more

More Than Moore

By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

How Reliable Is Your IP?

By Ed Sperling - 12 Sep, 2014 - Comments: 0

Almost everyone who has bought a new smartphone, car, home electronics device or appliance either has experienced technical glitches that require a replacement or repair, or they know someone who has experienced these problems. The good news is that only a very small fraction of the electronic glitches or failures can be contributed to hardware design. Most of it is due to manufacturing vari... » read more

Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes

By Navraj Nandra - 11 Sep, 2014 - Comments: 0

Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which not only reduce power but also actively manage the power during the course of the SoC (system on chip) activity, are emerging. This article describes these innovations from the foundation intellectua... » read more

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