How To Extend The ‘Unscalable’ RISC Architectures

By Rupert Baines - 24 Feb, 2022 - Comments: 0

A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled RISC Is Fundamentally Unscalable. This blog was really quite interesting and made some very good points about the limitations of a pure RISC design. The limitations of a pure RISC design It takes me back: some of my first marketing tasks were around the religious war between RISC ... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 15 Oct, 2021 - Comments: 0

Automotive Synopsys and 3D virtual-environment company Dassault Systèmes are collaborating on an automotive lighting system development platform. Synopsys’ optical design tools — LucidShape, LightTools, and CODE V — will be integrated with Dassault Systèmes' 3DEXPERIENCE Platform, which is used by automotive teams from different disciplines to work together on designs and simulations. ... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences

By Various Writers - 13 Oct, 2021 - Comments: 0

Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

Software-Hardware Co-Design Becomes Real

By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Working With RISC-V

By Ed Sperling - 17 Aug, 2021 - Comments: 0

RISC-V is coming on strong, but working with this open-source processor core isn't as simple as plugging in a commercial piece of IP. Zdenek Prikryl, CTO at Codasip, talks about utilizing hypervisors and open source tools and extensions to the RISC-V instruction set architecture, where design teams can run into problems, what will change as the architecture becomes more mature, the difference b... » read more

Is RISC-V The Future?

By Roddy Urquhart - 29 Jul, 2021 - Comments: 4

Is RISC-V the future? This is a question that we often get asked, and let’s assume that we mean ‘is RISC-V going to be the dominant ISA in the processor market?’ This is certainly an unfolding situation and has changed significantly in the last five years. RISC-V originated at the University of California, Berkeley, in 2010 and took a number of years to get traction with industry. A bi... » read more

A Methodology To Verify Functionality, Security, And Trust for RISC-V Cores

By OneSpin Solutions - 28 Jul, 2021 - Comments: 0

Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This paper describes a verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It... » read more

What Is An ASIP?

By Roddy Urquhart - 22 Apr, 2021 - Comments: 0

ASIP stands for “application-specific instruction-set processor” and simply means a processor which has been designed to be optimal for a particular application or domain. General-purpose versus application- or domain-specific processors Most processor cores to date have been general-purpose, which means that they have been designed to handle a wide range of applications with good average... » read more

What Does RISC-V Stand For?

By Roddy Urquhart - 29 Mar, 2021 - Comments: 1

RISC-V (pronounced “risk-five”) stands for ‘reduced instruction set computer (RISC) five’. The number five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981. The RISC concept (like the parallel MIPS development in Stanford University) was motivated by the fact that most processor instructions were not... » read more

A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing

By Codasip - 24 Mar, 2021 - Comments: 0

This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to co... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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