tag: KAIST

A HW-Based Correct Execution Environment Supporting Virtual Memory (Korea U., KAIST)
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "A Hardware-Based Correct Execution Environment Supporting Virtual Memory" was published by researchers at Korea University, Korea Advanced Institute of Science and Technology and other universities. Abstract "The rapid increase in data generation has led to outsourcing computation to cloud service providers, allowing clients to handle large tasks without inve... » read more

Chip Industry Technical Paper Roundup: August 20
By Linda Christensen - 20 Aug, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=252 /] More ReadingTechnical Paper Library home » read more

Reasons To Know IGZO
By Katherine Derbyshire - 15 Aug, 2024 - Comments: 0

Interest in monolithic 3D integration is driven by both compute-in-memory applications and a more general need for increased circuit density. Compute-in-memory architectures seek to reduce the power requirements of machine learning workloads, which are dominated by the movement of data between memory and logic components. Even in conventional architectures, though, placing high-density, high-ba... » read more

Potential Of 2D Semi-Metallic PtSe2 As Source/Drain Contacts For 2D Material FETs
By Technical Paper Link - 13 Aug, 2024 - Comments: 0

A technical paper titled “Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts” was published by researchers at Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University. Abstract: "In this ... » read more

Research Bits: July 22
By Jesse Allen - 22 Jul, 2024 - Comments: 0

Sub-1nm gate Researchers from Korea's Institute for Basic Science, Sungkyunkwan University, Harvard University, and Korea Advanced Institute of Science and Technology (KAIST) found a method that enables epitaxial growth of 1D metallic materials with a width of less than 1 nm, which they used as a gate electrode of a miniaturized transistor. The team controlled the crystal structure of molyb... » read more

How Simulation Addresses Hydrogen Fuel Challenges
By Kiyoung Jung - 18 Jul, 2024 - Comments: 0

By Kiyoung Jung and Kyutae Kim Hydrogen has gained the front seat as a fuel for carbon neutrality. The absence of carbon emission at the point of utilization makes it attractive for net-zero initiatives. Hydrogen fuel possesses qualities like higher flame speed (8x higher), lower ignition energy requirements (15x lower), and wider flammability limit (4% to 70%) compared to typical hydrocar... » read more

SRAM Security Concerns Grow
By Karen Heyman - 09 May, 2024 - Comments: 0

SRAM security concerns are intensifying as a combination of new and existing techniques allow hackers to tap into data for longer periods of time after a device is powered down. This is particularly alarming as the leading edge of design shifts from planar SoCs to heterogeneous systems in package, such as those used in AI or edge processing, where chiplets frequently have their own memory hi... » read more

Research Bits: April 8
By Jesse Allen - 08 Apr, 2024 - Comments: 0

Annealing processor Researchers from the Tokyo University of Science designed a scalable, fully-coupled annealing processor with 4096 spins on a single board with 36 CMOS chips, with parallelized capabilities for accelerated solving of combinatorial optimization problems. "We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing prepro... » read more

Building CFETs With Monolithic And Sequential 3D
By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

Chip Industry Technical Paper Roundup: Feb. 19
By Liz Allan - 19 Feb, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=199 /] More ReadingTechnical Paper Library home » read more

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