Chip Industry Week In Review


TSMC is expected to reduce its Fab 14 mature-node capacity by 15% to 20% to free up resources for its advanced packaging technologies, reports Counterpoint. The foundry will likely rely on its VIS affiliate site in Singapore (operational in late 2026) and other overseas fabs to ensure continued supply for older nodes. Memory The U.S. threatened 100% tariffs on South Korean memory compan... » read more

Annual Global IC Fabs And Facilities Report


Semiconductor companies announced a significant number of facilities in 2025 as global onshoring efforts continued across manufacturing, materials, packaging, design, and R&D. Investments came from both industry and government sources. Organizations worked together to solve current technology challenges, including soaring demand for AI chips and advanced memory, as well as complex applic... » read more

Chip Industry Technical Paper Roundup: Nov. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=492 /] Find more semiconductor research papers here. » read more

Free-Space Gated Transistor In Wide Bandgap And Ultra Wide Bandgap Semiconductors (KAUST Et Al.)


A new technical paper titled "Lateral Semiconductor–Free-Space Gate Transistors" was published by researchers at KAUST and the Indian Institute of Technology. Abstract "We introduce a novel lateral transistor architecture, the semiconductor−free-space gate transistor (SFGT), in which the conventional solid dielectric is replaced by a semiconductor−free-space gate configuration with su... » read more

Chip Industry Technical Paper Roundup: Oct. 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=486 /] Find more semiconductor research papers here. » read more

Six-Stack Vertically Integrated Hybrid Platform For Large Area Electronics (KAUST, Imperial College Et Al.)


A new technical paper titled "Three-dimensional integrated hybrid complementary circuits for large-area electronics" was published by researchers at KAUST, Imperial College London and the University of Manchester. Abstract "The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal o... » read more

Chip Industry Week in Review


Microsoft, OpenAI, and NVIDIA warned about power swings and physical damage to power grids increasing from AI training workloads and jointly proposed a multi-pronged approach to stabilize power in AI training data centers. Meanwhile, Anthropic issued a warning about the weaponization of agentic AI in a new 25-page Threat Intelligence report. Key concerns involve the evolution in AI-assisted ... » read more

Chip Industry Technical Paper Roundup: August 26


New technical papers recently added to Semiconductor Engineering’s library: [table id=467 /] Find more semiconductor research papers here. » read more

Nanofabrication Protocol That Allows Patterning Metallic Electrodes on 2D Materials Reliably (KAUST, National University of Singapore)


A new technical paper titled "High-yield photolithography protocol to pattern metallic electrodes on 2D materials without adhesive metallic layers" was published by researchers at KAUST and National University of Singapore. Abstract "When using two-dimensional (2D) materials to build electronic devices, adjacent metallic films need to be deposited to form electrodes. However, weak adhesion ... » read more

Chip Industry Week In Review


The EU’s tariffs on semiconductors will not exceed 15%, according to Trump’s latest trade deal. In addition, the EU committed to purchasing at least $40 billion worth of U.S. AI chips as well as other investments. [FAQ is here.] Lifelines for Intel: Intel inked a deal to sell the U.S. government a 10% non-voting equity stake in its business, worth $8.9 billion. The stake will be fun... » read more

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