Densification Of RF Designs


It’s challenging enough to deal with wireless signals at the 5G and 6G frequencies. But with increased density in chips crammed into smaller packages, higher power, beam forming, and MIMO, design requirements are very different than in the past. Simple parasitic extraction no longer is sufficient. Daren McClearnon, product manager for RF and microwave simulation at Keysight, talks about the n... » read more

Blog Review: Dec. 20


Siemens' Huw Geddes finds that the flexibility offered by the RISC-V ISA can introduce further verification and validation requirements to ensure that the combination of extensions and customization not just works but does not break anything else while delivering expected performance, plus looks at how processor trace can help. Cadence's Gustavo Araujo explains the various optimizations in t... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Synopsys acquired Imperas, pushing further into the RISC-V world with Imperas' virtual platform technology for verifying and emulating processors. Synopsys has been building up its RISC-V portfolio, starting with ARC-V processor IP and a full suite of tools introduced last month. The first high-NA EUV R&D center in the U.S. will be built at... » read more

What Is SMU Digitizer Mode And Why Is It Useful?


Some source/measure unit (SMU) products support a feature called “digitizer mode.” However, from the title alone it is not obvious exactly what this feature means. This capability is related to the triggering system of the SMU, so it is helpful to review the ARM-TRIGGER model first. Keysight products supporting the standard commands for programmable instrument (SCPI) adhere to the trigge... » read more

Using Keysight Design Data Management SOS In The Cloud


Integrated circuits (ICs) are becoming increasingly complex and resource intensive. This is challenging companies to design chips more efficiently and reduce the overall impact of peak processing loads. Companies typically use large server farms and high-performance storage systems to design and validate chips quickly and efficiently. However, this approach is very resource intensive. For ex... » read more

Blog Review: December 13


Synopsys' Charles Dittmer discusses key and emerging use cases for Bluetooth Low Energy and how combining BLE with other wireless protocols can open new avenues of functionality for application areas including automotive, hearables, and retail. Cadence's Neelabh Singh points out changes in the terminologies describing USB4 links and shows the various possible link configurations put forth by... » read more

Auto Network Speeds Rise As Carmakers Prep For Autonomy


In-vehicle networks are starting to migrate from domain architectures to zonal architectures, an approach that will simplify and speed up communication in a vehicle using fewer protocols, less wiring, and ultimately lower cost. Zonal architectures will partition vehicles into zones that are more manageable and flexible, but getting there will take time. There is so much legacy technology in ... » read more

Blog Review: Dec. 6


Cadence's Vinod Khera checks out potential implications of generative AI for EDA, including how it could increase the learning rate of students and reduce the rising verification cost. Synopsys' Kiran Vittal considers the driving factors behind RISC-V's growth and why it is becoming increasingly important for applications ranging from automotive to 5G mobile, AI, and data centers. Siemens... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

System State Challenges Widen


Knowing the state of a system is essential for many analysis and debug tasks, but it's becoming more difficult in heterogeneous systems that are crammed with an increasing array of features. There is a limit as to how many things engineers can keep track of, and the complexity of today's systems extends far beyond that. Hierarchy and abstraction are used to help focus on the important aspect... » read more

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