tag: KLA-Tencor

High-Volume Manufacturing Device Overlay Process Control
By KLA - 20 Jun, 2018 - Comments: 0

By Honggoo Leea, Sangjun Hana, Jaeson Wooa, DongYoung Leea, ChangRock Songa, Hoyoung Heob, Irina Brinsterb, DongSub Choic, John C. Robinsonb aSK Hynix, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do, 467-701, Korea bKLA-Tencor Corp., 8834 N. Capital of Texas Hwy, Austin, TX 78759 cKLA-Tencor Korea, Starplaza bldg.., 53 Metapolis-ro, Hwasung City, Gyeonggi-do, Korea Abstract ... » read more

200mm Fab Crunch
By Mark LaPedus - 21 May, 2018 - Comments: 2

Growing demand for analog, MEMS and RF chips continues to cause acute shortages for both 200mm fab capacity and equipment, and it shows no sign of letting up. Today, 200mm fab capacity is tight with a similar situation projected for the second half of 2018 and perhaps well into 2019. In fact, 2018 will likely represent the third consecutive year that 200mm fab capacity will be tight. The sam... » read more

What’s Missing In EUV?
By Mark LaPedus - 17 May, 2018 - Comments: 0

Extreme ultraviolet (EUV) lithography is expected to move into production at 7nm and/or 5nm, but as previously reported, there are some gaps in the arena. At one time, the power source was the big problem, but that appears to be solved in the near term. Now, a phenomenon called stochastic effects, or random variations, are the biggest challenge for EUV lithography. But at most events, th... » read more

FinFET Metrology Challenges Grow
By Mark LaPedus - 17 May, 2018 - Comments: 1

Chipmakers face a multitude of challenges in the fab at 10nm/7nm and beyond, but one technology that is typically under the radar is becoming especially difficult—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems in devices and processes. It helps to ensure yields in both the lab and fab. At 28nm and above, metrology is a straightforward... » read more

The Challenges Of Process Control On FinFETs And FD-SOI
By Jeff Barnum - 17 May, 2018 - Comments: 0

Across the semiconductor industry, both FD-SOI and finFET transistor technologies are in high volume production, with IC manufacturers looking to extend both technologies to gain additional performance improvements and meet the variety of customer specific technical and economic requirements. In developing the processes needed for the next-generation FD-SOI and finFET technologies, both transis... » read more

Innovative Scalable Design-Based Care Area Methodology For Defect Monitoring In Production
By KLA - 17 May, 2018 - Comments: 0

By Ian Tolle, GlobalFoundries, and Ankit Jain, KLA-Tencor Abstract The use of design-based care areas on inspection tools [1, 2] to characterize defects has been well established in recent years. However, the implementation has generally been limited to specific engineering use cases, due to the complexity involved with care area creation and inspection recipe setup. Furthermore, creating, ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 11 May, 2018 - Comments: 0

Test and packaging In a major surprise, Cohu has entered into a definitive agreement to acquire Xcerra for approximately $796 million. With the deal, Cohu will enter the ATE market. Last year, a group from China entered into a definitive agreement under which it would acquire Xcerra. But the U.S. blocked Xcerra’s sale to the Chinese group. Ironically, at one time, Cohu was reportedly lobbyin... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 27 Apr, 2018 - Comments: 0

Chipmakers As reported, Intel is struggling at 10nm. Intel already has encountered some difficulties, as the chip giant late last year pushed out the volume ramp of its new 10nm process from the second half of 2017 to the first part of 2018, according to analysts. Intel continues to struggle with 10nm, and has delayed the volume ramp again, according to multiple reports. During its earnings... » read more

Next EUV Issue: Mask 3D Effects
By Mark LaPedus - 25 Apr, 2018 - Comments: 6

As extreme ultraviolet (EUV) lithography moves closer to production, the industry is paying more attention to a problematic phenomenon called mask 3D effects. Mask 3D effects involve the photomask for EUV. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scan... » read more

Criticality of Wafer Edge Inspection and Metrology Data to All-Surface Defectivity Root Cause and Yield Analysis
By KLA - 19 Apr, 2018 - Comments: 0

Abstract As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi-film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, ... » read more

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