Mass Producing Qubits (Imec and KU Leuven)


This new technical paper titled "Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms" was published by researchers at Imec and KU Leuven. Abstract "As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become app... » read more

Security Research: Technical Paper Round-Up


A number of hardware security-related technical papers were presented at recent conferences, including the August 2022 USENIX Security Symposium and IEEE’s International Symposium on Hardware Oriented Security and Trust (HOST). Topics include side-channel attacks and defenses (including on-chip mesh interconnect attacks), heterogeneous attacks on cache hierarchies, rowhammer attacks and mitig... » read more

Heterogenous Computing & Cache Attacks


Researchers at imec-COSIC, KU Leuven presented this paper titled "Double Trouble: Combined Heterogeneous Attacks on Non-Inclusive Cache Hierarchies" at the USENIX Security Symposium in Boston in August 2022. Note, this is a prepublication paper. Abstract: "As the performance of general-purpose processors faces diminishing improvements, computing systems are increasingly equipped with domai... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing, connectivity Semtech Corporation announced that it will acquire Sierra Wireless, an IoT services company. The acquisition will combine Semtech’s LoRa end nodes and cloud service with Sierra Wireless’ cellular capabilities. Telit will incorporate Thales’s cellular IoT products business under a new name Telit Cinterion, led by Telit. Telit Cinterion will be Californ... » read more

High-NA EUV May Be Closer Than It Appears


High-NA EUV is on track to enable scaling down to the Angstrom level, setting the stage for chips with even higher transistor counts and a whole new wave of tools, materials, and system architectures. At the recent SPIE Advanced Lithography conference, Mark Phillips, director of lithography hardware and solutions at Intel, reiterated the company’s intention to deploy the technology in high... » read more

Silicon Verified ASIC Implementation for Saber


New research paper from Purdue University, KU Leuven, and Intel Labs titled "A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator." Abstract: "National Institute of Standard & Technology (NIST) is currently running a multi-year-long standardization procedure to select quantum-safe or post-quantum cryptographic schemes to be used in the future. Saber is the... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Fraunhofer IIS has opened a five-kilometer (3.11-mile) 5G test bed for automotive 5G applications near the city of Rosenheim in Bavaria, Germany. A closed 5G network with multiple base stations covers the test track, where connected cars can be tested under real conditions. “The automotive test bed is designed specially for developers and users that want to test new conn... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs UMC plans to build a new fab next to its existing 300mm fab in Singapore. The new fab, called Fab12i P3, will manufacture wafers based on UMC’s 22nm/28nm processes. The planned investment for this project will be $5 billion. The first phase of this greenfield fab will have a monthly capacity of 30,000 wafers with production expected to commence in late 2024. To account fo... » read more

Photomask Challenges At 3nm And Beyond


Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Why Mask Blanks Are Critical


Geoff Akiki, president of Hoya LSI at the Hoya Group, sat down with Semiconductor Engineering to talk about optical and extreme ultraviolet (EUV) lithography as well as mask blanks. What follows are excerpts of that discussion. SE: Mask blanks are components that serve as the base or the substrate for a photomask. Why are they critical? Akiki: If you look at Hoya, we've been positioned as... » read more

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