tag: KU Leuven

Silicon Verified ASIC Implementation for Saber
By Technical Paper Link - 13 May, 2022 - Comments: 0

New research paper from Purdue University, KU Leuven, and Intel Labs titled "A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator." Abstract: "National Institute of Standard & Technology (NIST) is currently running a multi-year-long standardization procedure to select quantum-safe or post-quantum cryptographic schemes to be used in the future. Saber is the... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 13 May, 2022 - Comments: 0

Automotive, mobility Fraunhofer IIS has opened a five-kilometer (3.11-mile) 5G test bed for automotive 5G applications near the city of Rosenheim in Bavaria, Germany. A closed 5G network with multiple base stations covers the test track, where connected cars can be tested under real conditions. “The automotive test bed is designed specially for developers and users that want to test new conn... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 25 Feb, 2022 - Comments: 0

Chipmakers, OEMs UMC plans to build a new fab next to its existing 300mm fab in Singapore. The new fab, called Fab12i P3, will manufacture wafers based on UMC’s 22nm/28nm processes. The planned investment for this project will be $5 billion. The first phase of this greenfield fab will have a monthly capacity of 30,000 wafers with production expected to commence in late 2024. To account fo... » read more

Photomask Challenges At 3nm And Beyond
By Mark LaPedus - 25 Jan, 2022 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss optical and EUV photomasks issues, as well as the challenges facing the mask business, with Naoya Hayashi, research fellow at DNP; Peter Buck, director of MPC & mask defect management at Siemens Digital Industries Software; Bryan Kasprowicz, senior director of technical strategy at Hoya; and Aki Fujimura, CEO of D2S. What f... » read more

Why Mask Blanks Are Critical
By Mark LaPedus - 21 Oct, 2021 - Comments: 1

Geoff Akiki, president of Hoya LSI at the Hoya Group, sat down with Semiconductor Engineering to talk about optical and extreme ultraviolet (EUV) lithography as well as mask blanks. What follows are excerpts of that discussion. SE: Mask blanks are components that serve as the base or the substrate for a photomask. Why are they critical? Akiki: If you look at Hoya, we've been positioned as... » read more

EUV Pellicles Finally Ready
By Mark LaPedus - 22 Mar, 2021 - Comments: 0

After a period of delays, EUV pellicles are emerging and becoming a requirement in high-volume production of critical chips. At the same time, the pellicle landscape for extreme ultraviolet (EUV) lithography is changing. ASML, the sole supplier of EUV pellicles, is transferring the assembly and distribution of these products to Mitsui. Others are also developing pellicles for EUV, a next-gen... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Challenges Linger For EUV
By Mark LaPedus - 11 Nov, 2020 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

Manufacturing Bits: May 26
By Mark LaPedus - 26 May, 2020 - Comments: 0

7-level nanosheets The 2020 Symposia on VLSI Technology & Circuits for the first time will be held as a virtual conference. The event, to be held from June 15-18, is organized around the theme “The Next 40 Years of VLSI for Ubiquitous Intelligence.” Among the papers at the event include advanced nanosheet transistors, 3D stacked memory devices and even an artificial iris. At the ... » read more

Making Sense Of PUFs
By Bryon Moyer - 07 May, 2020 - Comments: 3

As security becomes a principal design consideration, physically unclonable functions (PUFs) are seeing renewed interest as new players emerge onto the market. PUFs can play a central role in hardware roots of trust (HRoTs), but the messaging in the market can make it confusing to understand the different types of PUF as well as their pros and cons. PUFs leverage some uncertain aspect of som... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy