Blog Review: Jan. 24


Mentor's Rich Edelman shares some tips for debugging complex UVM testbenches containing multiple agents, multiple checkers, and new HDL. Synopsys' Prasad Subudhi K. S. explains the PCIe PIPE 4.4.1 specification and the major improvements since 4.3, including better optimization in data flow and ultra-low power operations. Cadence's Paul McLellan steps back to before the Meltdown and Spect... » read more

Nodes Vs. Nodelets


Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers. There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or "node-lets" being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm. Node-lets ar... » read more

The Week In Review: Manufacturing


Market research The SEMI Industry Strategy Symposium (ISS) opened with the theme “Smart, Intuitive & Connected: Semiconductor Devices Transforming the World.” Click here for some of the highlights at ISS. Here are more highlights from ISS. Korea is on a spending spree for fab tools. In total, Samsung and SK Hynix are forecast to invest over $20 billion in fab tools worldwide in 2018... » read more

Robots Get Social


From Star Trek’s Data to Star Wars’ C-3PO, the idea of humanoid robots has fascinated people for years. Back in the real world, robots build automobiles in factories, mow lawns, and even assist in complex heart surgery. Meanwhile, the use of androids like Data is approaching reality, as semiconductor and semiconductor-related devices like low-power microprocessors, 3D sensors, accelerometer... » read more

The Next 5 Years Of Chip Technology


Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

Blog Review: Jan. 10


Rambus' Aharon Etengoff explains the Meltdown and Spectre CPU vulnerabilities and why they could negatively affect the semiconductor industry for decades. Cadence's Paul McLellan has an explainer on Meltdown and how it's an unintended consequence of a processor behaving as intended. Mentor's Ruben Ghulghazaryan and Jeff Wilson investigate using machine learning to predict post-deposition ... » read more

Packaging Challenges For 2018


The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Blog Review: Jan. 3


Ansys' Steve Pytel argues that increased signaling speeds and frequencies have led to signal integrity issues that circuit simulation alone cannot handle. Cadence's Paul McLellan dives into the details of Intel's 10nm process, including three layers of self-aligned quadruple patterning, contact-over-active-gate, and cobalt for contact fill. Mentor's Ron Press and Vidya Neerkundar argue th... » read more

A New Memory Contender?


Momentum is building for a new class of ferroelectric memories that could alter the next-generation memory landscape. Generally, ferroelectrics are associated with a memory type called ferroelectric RAMs (FRAMs). Rolled out by several vendors in the late 1990s, FRAMs are low-power, nonvolatile devices, but they are also limited to niche applications and unable to scale beyond 130nm. While... » read more

What the Experts Think


Coventor recently sponsored an expert panel discussion at IEDM 2017 to discuss how we might advance the semiconductor industry into the next generation of technology. The panel discussed alternative methods to solve fundamental problems of technology scaling, using advances in semiconductor architectures, patterning, metrology, advanced process control, variation reduction, co-optimization and ... » read more

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