tag: Lam Research

Blog Review: May 3
By Jesse Allen - 03 May, 2017 - Comments: 0

Cadence's Paul McLellan shares highlights from a recent IRDS panel, including changing the assumptions about computing and looking for the next "killer app." Synopsys' Meenakshy Ramachandran introduces the array of improvements in HDMI 2.1, from higher bandwidth to Dynamic HDR. Mentor's Minghui Fan checks out advancements in optical proximity correction and resolution enhancement technolo... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 21 Apr, 2017 - Comments: 0

Fab tool vendors In the wafer fab equipment (WFE) rankings, Applied Materials was the leader in terms of market share in 2016, according to Gartner. For WFE, Lam Research jumped from fourth place in 2015 to second place in the rankings in 2016, according to Gartner. ASML was third, followed by TEL. Meanwhile, VLSI Research recently released its ranking for both front-end and backend equipment.... » read more

Moore’s Law: A Status Report
By Ed Sperling - 20 Apr, 2017 - Comments: 3

Moore's Law has been synonymous with "smaller, faster, cheaper" for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs. This does not make [getkc id="74" comment="Moore's Law"] any less relevant. The number of companies racing from 16/14nm to 7nm is higher t... » read more

Blog Review: April 19
By Jesse Allen - 19 Apr, 2017 - Comments: 0

Mentor's Tom Fitzpatrick explains what the Portable Stimulus standard will do, what it won't, and why the choice of input language defined by the standard matters. Cadence's Paul McLellan listens in as IRDS chairman Paolo Gargini explains how long it takes technology breakthroughs to make out of the lab and into high-volume manufacturing. Synopsys' Robert Vamosi points to the recent sound... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 14 Apr, 2017 - Comments: 0

Fab equipment and test VLSI Research has released its top 10 semiconductor equipment supplier ranking in terms of sales in 2016. Applied Materials topped the list again, achieving a growth of 18%. ASML was second, followed by Lam Research, TEL and KLA-Tencor. Fig. 1: Ranking based on 2016 sales. Source: VLSI Research. Unic Capital Management, a Chinese-based private equity fund, announ... » read more

Electroplating IC Packages
By Mark LaPedus - 10 Apr, 2017 - Comments: 2

The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. [getentity id="22817" e_name="Applied Materials"]  recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging. ECD—sometimes referred to as pl... » read more

Blog Review: April 5
By Jesse Allen - 05 Apr, 2017 - Comments: 0

In a video, Cadence's Megha Daga digs into the different architectural layers present in convolutional neural networks and how they contribute to object detection and classification in a real world scenario. Mentor's Mike Santarini argues that as things become increasingly connected, the stakes of bad design and bad verification are higher than they've ever been. Synopsys' Robert Vamosi w... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 31 Mar, 2017 - Comments: 0

Chipmakers At an event, Intel’s Technology and Manufacturing group outlined the company's vision. As part of the event, Intel reiterated what many are saying—the current node designations are meaningless and misleading. “For example, Intel estimates that its 14nm solution that has been out in the market since 2014 should be equal to 10nm solutions released by competitors in the near futu... » read more

Blog Review: March 22
By Jesse Allen - 22 Mar, 2017 - Comments: 0

Cadence's Paul McLellan shares TSMC's plans for 5nm and gate-all-around FET, plus other highlights from last week's Technology Symposium. Mentor's Craig Armenti examines how product development teams can increase efficiency through concurrent schematic design. Synopsys' Jim Ivers warns of the data security and privacy issues posed by a wave of popular connected toys. At Embedded World,... » read more

Patterning Problems Pile Up
By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy