tag: Leti

Chip Industry’s Technical Paper Roundup: Oct 25
By Linda Christensen - 25 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=59 /] » read more

What’s Different About Next-Gen Transistors
By Katherine Derbyshire - 20 Oct, 2022 - Comments: 0

After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node. Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-aroun... » read more

On-chip 2D/3D Photonics Integration Solution Using Deposited Polycrystalline Silicon for Optical Interconnects Applications
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Polycrystalline silicon PhC cavities for CMOS on-chip integration" was published by researchers at Tyndall National Institute, Munster Technological University, and Université Grenoble Alpes, CEA, LETI. "In this work, we present an on-chip 2D and 3D photonics integration solution compatible with Front End of Line integration (FEOL) using deposited polycrystalli... » read more

Chip Industry’s Technical Paper Roundup: Oct. 4
By Linda Christensen - 04 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=55 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Adaptive Memristive Hardware
By Technical Paper Link - 02 Oct, 2022 - Comments: 0

A new technical paper titled "Self-organization of an inhomogeneous memristive hardware for sequence learning" was just published by researchers at University of Zurich, ETH Zurich, Université Grenoble Alpes, CEA, Leti and Toshiba. "We design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorp... » read more

Spin–Orbit Qubit With A Single Hole Electrostatically Confined In A Natural Silicon Metal-Oxide-Semiconductor Device
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "A single hole spin with enhanced coherence in natural silicon" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Semiconductor spin qubits based on spin–orbit states are responsive to electric field excitations, allowing for practical, fast and potentially scalable qubit control. Spin electric susceptibility, however,... » read more

Hybrid Bonding Moves Into The Fast Lane
By Laura Peters - 21 Jul, 2022 - Comments: 1

The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

Technical Paper Round-Up: June 21
By Linda Christensen - 21 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=34 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

End-to-End System for Object Localization By Coupling pMUTs to a Neuromorphic RRAM-based Computational Map
By Technical Paper Link - 20 Jun, 2022 - Comments: 0

New research paper titled "Neuromorphic object localization using resistive memories and ultrasonic transducers" from researchers at CEA, LETI, Université Grenoble Alpes and others. Abstract "Real-world sensory-processing applications require compact, low-latency, and low-power computing systems. Enabled by their in-memory event-driven computing abilities, hybrid memristive-Complementary... » read more

Next-Gen 3D Chip/Packaging Race Begins
By Mark LaPedus - 31 Jan, 2022 - Comments: 5

The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages. AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips usin... » read more

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