Overlay Challenges On The Rise

By Mark LaPedus - 16 Nov, 2017 - Comments: 2

The overlay metrology equipment market is heating up at advanced nodes as the number of masking layers grows and the size of the features that need to be aligned continue to shrink. Both ASML and KLA-Tencor recently introduced new [getkc id="307" kc_name="overlay"] metrology systems, seeking to address the increasing precision required for lines, cuts and other features on each layer. At 10/... » read more

Searching For EUV Mask Defects

By Mark LaPedus - 19 Oct, 2017 - Comments: 2

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this technology can be used in production. One lingering issue that is becoming more worrisome is how to find [gettech id="31045" comment="EUV"] mask defects. That isn't the only issue, of course. The industry continues to work on the power source and resists. Bu... » read more

Looming Issues And Tradeoffs For EUV

By Mark LaPedus - 25 Sep, 2017 - Comments: 5

Momentum is building for extreme ultraviolet (EUV) lithography, but there are still some major challenges to solve before this long-overdue technology can be used for mass production. [gettech id="31045" comment="EUV"] lithography—a next-generation technology that patterns tiny features on a chip—was supposed to move into production around 2012. But over the years, EUV has encountered se... » read more

Unsolved Litho Issues At 7nm

By Ed Sperling - 21 Sep, 2017 - Comments: 1

By Ed Sperling & Mark LaPedus EUV lithography is creating a new set of challenges on the photomask side for which there currently are no simple solutions. While lithography is viewed as a single technology, [gettech id="31045" comment="EUV"] actually is a collection of technologies. Not all of those technologies have advanced equally and simultaneously, however. For example, aberrations... » read more

Inside Panel-Level Fan-Out Technology

By Mark LaPedus - 11 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology with Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM, and Michael Töpper, business development manager at Fraunhofer IZM. Braun is responsible for the Panel Level Packaging Consortium at Fraunhofer IZM, as well as the group manager for assembly and encap... » read more

What’s Changing At BACUS

By Jan Willis - 17 Aug, 2017 - Comments: 0

Jim Wiley, president of SPIE BACUS, talks about this year's merger of the EUV Lithography Symposium and the SPIE Photomask Conference—including what's new and different, the latest updates on the event location, and topics to look forward to such as EUV mask inspection—as well as his predictions on machine learning. https://youtu.be/GNxUmMAU9zs » read more

What’s After FinFETs?

By Mark LaPedus - 24 Jul, 2017 - Comments: 3

Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

Is 7nm The Last Major Node?

By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

Tech Talk: 7nm Litho

By Ed Sperling - 20 Jul, 2017 - Comments: 2

David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types. https://youtu.be/FBnYRAL1xKY Related Stories Inside Next-Gen Transistors Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes & the state of semiconductor development in China. Faster Time T... » read more

Inside FD-SOI And Scaling

By Mark LaPedus - 15 Jun, 2017 - Comments: 5

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

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tag: lithography

Overlay Challenges On The Rise

Searching For EUV Mask Defects

Looming Issues And Tradeoffs For EUV

Unsolved Litho Issues At 7nm

Inside Panel-Level Fan-Out Technology

What’s Changing At BACUS

What’s After FinFETs?

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