tag: lithography

Inside Panel-Level Fan-Out Technology
By Mark LaPedus - 11 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology with Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM, and Michael Töpper, business development manager at Fraunhofer IZM. Braun is responsible for the Panel Level Packaging Consortium at Fraunhofer IZM, as well as the group manager for assembly and encap... » read more

What’s Changing At BACUS
By Jan Willis - 17 Aug, 2017 - Comments: 0

Jim Wiley, president of SPIE BACUS, talks about this year's merger of the EUV Lithography Symposium and the SPIE Photomask Conference—including what's new and different, the latest updates on the event location, and topics to look forward to such as EUV mask inspection—as well as his predictions on machine learning. https://youtu.be/GNxUmMAU9zs » read more

What’s After FinFETs?
By Mark LaPedus - 24 Jul, 2017 - Comments: 3

Chipmakers are readying their next-generation technologies based on 10nm and/or 7nm finFETs, but it's still not clear how long the finFET will last, how long the 10nm and 7nm nodes for high-end devices will be extended, and what comes next. The industry faces a multitude of uncertainties and challenges at 5nm, 3nm and beyond. Even today, traditional chip scaling continues to slow as process ... » read more

Is 7nm The Last Major Node?
By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

Tech Talk: 7nm Litho
By Ed Sperling - 20 Jul, 2017 - Comments: 2

David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types. https://youtu.be/FBnYRAL1xKY Related Stories Inside Next-Gen Transistors Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes & the state of semiconductor development in China. Faster Time T... » read more

Inside FD-SOI And Scaling
By Mark LaPedus - 15 Jun, 2017 - Comments: 5

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

High-Stakes Litho Game
By Ed Sperling - 18 May, 2017 - Comments: 0

The commercial introduction of EUV looks all but assured these days. There is enough history to show it works. Uptime and throughput are improving, and systems are shipping today. The question now is how to measure its success. In the short-term, this is a fairly simple financial exercise for companies like ASML and Zeiss, which have been closely collaborating to get these massive systems ou... » read more

Extending EUV Beyond 3nm
By Ed Sperling - 18 May, 2017 - Comments: 10

Jan van Schoot, senior principal architect at [getentity id="22935" comment="ASML"], sat down with Semiconductor Engineering to talk about how far EUV can be extended and where it is today. What follows are excerpts of that discussion. SE: High numerical aperture [gettech id="31045" comment="EUV"] has been in the works for some time as a way of extending EUV. How is this technology shaping... » read more

Moore’s Law: A Status Report
By Ed Sperling - 20 Apr, 2017 - Comments: 3

Moore's Law has been synonymous with "smaller, faster, cheaper" for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs. This does not make [getkc id="74" comment="Moore's Law"] any less relevant. The number of companies racing from 16/14nm to 7nm is higher t... » read more

Biz Talk: ASICs
By Ed Sperling - 27 Mar, 2017 - Comments: 0

eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

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