New Tools Enabling The Internet of Things

By Frank Schirrmeister - 25 Sep, 2014 - Comments: 0

Last week I attended CDNLive Boston as a speaker and was really looking forward to the keynote given by Samuel H. Fuller, CTO and VP of R&D at Analog Devices, called “The Third Exponential Wave and the Challenges Ahead”. It was great to see, re-affirmed by Dr. Fuller, a lot of my thoughts about the Internet of Things and how it requires new tools in EDA. This, by the way, conveniently t... » read more

Implementation Challenges And Solutions Of Low-Power, High-Performance Memory Systems

By Rambus - 10 Sep, 2014 - Comments: 0

Mobile devices and their demand for rapid innovation have fundamentally and forever changed the semiconductor industry. These devices have fueled tremendous innovation in the last few years to bring about drastic improvements in performance, power and cost efficiency. They also demand condensed product development cycles which accelerate the rate and need for innovation. The only thing that has... » read more

Tech Talk: Near Threshold Computing 2

By Ed Sperling - 27 Aug, 2014 - Comments: 0

ARM Fellow Rob Aitken walks through the details of near-threshold computing and why it's such an important consideration at established process nodes. [youtube vid=lvfu54_JwEg] » read more

Tech Talk: Near Threshold Computing

By Ed Sperling - 07 Aug, 2014 - Comments: 1

ARM fellow Rob Aitken talks about what is NTC, why it has taken so long to catch on, and the enormous energy savings possible using this technique at established process nodes. [youtube vid=Ersdl81yTnM] » read more

FinFET Based Designs: Reliability Verification Implications

By Aveek Sarkar - 10 Jul, 2014 - Comments: 1

Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overa... » read more

Can HLS Be Trusted?

By Brian Bailey - 08 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Mike Meredith, solutions architect at Cadence/Forte Design Systems; Mark Warren, Solutions Group director at Cadence; Thomas Bollaert, vice president of application engineering at Calypto; and Devadas Varma, senior director at Xilinx. Part 1 of the discussion looked at the changing market for HLS and the types of customers who are adopting HLS today. Divi... » read more

Power Management Techniques For Smart Grid Devices

By Various Writers - 07 May, 2014 - Comments: 0

Energy efficiency is a top concern among developers building connected devices for the smart grid. Initially, the application-centric approach to building a device was used. But today, with sophisticated hardware power management features available on most modern processors, this is no longer the case. What’s needed is an OS-level approach that allows developers to take advantage of the full ... » read more

Formal Verification Of Power-Aware Designs Using JasperGold Low Power Verification App

By Various Writers - 07 May, 2014 - Comments: 1

Power reduction and management methods are now all-pervasive in system-on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design, th... » read more

Leveraging Processor Extensibility To Build An Ultra Low-Power Embedded Subsystem

By Various Writers - 07 May, 2014 - Comments: 0

There is increasing demand for electronic devices to execute more functions while consuming less power and silicon area. To achieve this, systems instantiating multiple, heterogeneous processor cores optimized for low power and high performance are gaining popularity among design teams. In these systems, one or more deeply embedded processors execute a limited set of dedicated applications. The... » read more

Choosing The Right Systems Design Path

By Brian Fuller - 13 Feb, 2014 - Comments: 0

I’m a cheap bastard, usually given to self-abnegation when it comes to buying material goods for myself. But I broke down and bought a runner’s watch late last year because I wanted to change up my exercise routine to run the same distances, only faster. I quickly decided against going all in and getting a GPS watch. At this point in the arc of electronics-design technology, it’s hard ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: low power