tag: low power

Bit Mapping
By Ed Sperling - 22 Feb, 2013 - Comments: 0

The rule of thumb for semiconductor manufacturing is that big breakthroughs tend to last a decade, or about five process nodes. While the transistor already has spanned more than five decades and the IC more than four decades, the technology used to create them typically only lasts about one. 193nm lithography has been around more than a decade. Bets were being made publicly back at 45nm—o... » read more

New Issues In Signoff
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

RTL Design-For-Power Methodology
By Various Writers - 14 Feb, 2013 - Comments: 0

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To download this white paper, click here. » read more

Big Rocks First
By Synopsys - 14 Feb, 2013 - Comments: 0

By Cary Chin Up on the wall in the hallway by the printer at my office, there’s an article by a management consultant entitled, “PUT THE BIG ROCKS IN FIRST!” It describes the demonstration that has been conducted and described many times by many consultants and motivational speakers over the years. Starting with an empty bucket, place large rocks in the bucket until it is full. Repeat by... » read more

Clean Your Clock
By William Ruby - 14 Feb, 2013 - Comments: 0

Lowering power consumption seems to be on every designer’s mind these days. And yet when asked about applying low-power design techniques, many engineers respond, “Well, we do clock gating ... and that’s about it.” Clock gating is low-hanging fruit when it comes to low-power design. Clock gating is also well automated, as witnessed by capabilities in modern logic synthesis tools. The... » read more

Tech Talk: LP Design And Verification
By Ed Sperling - 06 Dec, 2012 - Comments: 0

Cadence's Qi Wang talks with Low-Power/High-Performance Engineering about power formats and what else can be done to save power in SoCs. [youtube vid=afJ6VQ0AYgg] » read more

Watch Out For The Cliff
By Synopsys - 06 Dec, 2012 - Comments: 0

By Cary Chin (to be sung to the tune of “George of the Jungle”) Along with superstorms, a still-limping economy, and people launching missiles and mortars at each other, the headline news of the day continues to include the impending "fiscal cliff." This is a completely artificial event that we created for ourselves more than 10 years ago, and it has been on our calendar ever since. It's ... » read more

The Trouble With Clock Trees
By Arvind Narayanan - 11 Oct, 2012 - Comments: 0

By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more

ST’s FD-SOI Tech Available to All Through GF
By Various Writers - 08 Oct, 2012 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice Pres... » read more

LP Test Strategies
By Luke Lang - 13 Sep, 2012 - Comments: 0

By Luke Lang Power during test is one area that is often overlooked. In the worst (but easiest to diagnose) case, excessive test power can lead to a smoking chip on the tester. (You don’t need an engineering education to see the problem.) In a better (but more difficult to diagnose) case, excessive test power will cause reduced yield. Let’s look at what causes excessive test power and how ... » read more

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