tag: low power

Ternary LIM Operation of the TNAND and TNOR Universal Gates Using DG Feedback FETs
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "Logic-in-Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double-Gated Feedback Field-Effect Transistors" was published by researchers at Korea University. Abstract "In this study, the logic-in-memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double-gated feedback field-effect transistors. The component transistor... » read more

Improving Performance And Power With HBM3
By Andy Patrizio - 30 Jan, 2023 - Comments: 0

HBM3 swings open the door to significantly faster data movement between memory and processors, reducing the power it takes to send and receive signals and boosting the performance of systems where high data throughput is required. But using this memory is expensive and complicated, and that likely will continue to be the case in the short term. High Bandwidth Memory 3 (HBM3) is the most rece... » read more

What Designers Need To Know About USB Low-Power States
By Synopsys - 11 Jan, 2023 - Comments: 0

In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond t... » read more

Addressing Three Big Challenges In Silicon Realization
By Bradley Geden - 22 Nov, 2022 - Comments: 0

There is no better way to gain insight into prevailing technical challenges than bringing together industry experts to share experiences and proposed solutions. Silicon realization—the ability to design and build today’s complex semiconductors—is one domain with no shortage of challenges. The quest for the best power, performance, and area, and delivery of first-time-right silicon, requir... » read more

Accelerating IoT Designs: Designing For Low Power In The Era Of Smart Everything
By Ron Lowman - 10 Nov, 2022 - Comments: 0

Most of us have become accustomed to interacting with the ubiquitous technology ecosystem daily (if not hourly). From fitness trackers, smart vacuums, and semi-autonomous vehicles to the smart home devices that wake us up every morning, there’s no denying that the internet of things (IoT) boom has proliferated in every aspect of our lives. At the core of this instant, at-our-fingertips conn... » read more

How Low Can You Go? Pushing The Limits Of Transistors
By Synopsys - 09 Nov, 2022 - Comments: 0

Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when the device is not active (leakage power). This highly competitive industry provides significant rewar... » read more

Improving the Electrical Performance and Low-Frequency Noise Properties of p-Type TFET
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Effect of high-pressure D2 and H2 annealing on LFN properties in FD-SOI pTFET" was published by researchers at Chungnam National University and Korea Polytechnic College. "This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silic... » read more

A Power-First Approach
By Brian Bailey - 27 Oct, 2022 - Comments: 7

It is becoming evidently clear that heat will be the limiter for the future of semiconductors. Already, large percentages of a chip are dark at any time, because if everything operated at the same time the amount of heat generated would exceed the ability of the chip and package to dissipate that energy. If we now start to contemplate stacking dies, where the ability to extract heat remains con... » read more

Using Silicon Photonics To Reduce Latency On Edge Devices
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new technical paper titled "Delocalized photonic deep learning on the internet’s edge" was published by researchers at MIT and Nokia Corporation. “Every time you want to run a neural network, you have to run the program, and how fast you can run the program depends on how fast you can pipe the program in from memory. Our pipe is massive — it corresponds to sending a full feature-leng... » read more

Simplifying AI Edge Deployment
By Ed Sperling - 10 Oct, 2022 - Comments: 0

Barrie Mullins, vice president of product at Flex Logix, explains how a programmable accelerator chip can simplify semiconductor design at the edge, where chips need to be high performance as well as low power, yet developing everything from scratch is too expensive and time-consuming. Programmability allows these systems to stay current with changes in algorithms, which can affect everything f... » read more

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