Towards Decarbonization: Keeping Electronics Energy Consumption In Check

By Frank Schirrmeister - 23 Nov, 2021 - Comments: 0

The International Technology Roadmap for Semiconductors (ITRS) roadmap famously said in 2001 that "cost of design is the greatest threat to the continuation of the semiconductor roadmap." For years, the industry followed the ITRS updates on productivity improvements provided by automating design and hardware to counteract the looming design cost. The discussion on decarbonization has some simil... » read more

Low-Power Always-On Circuits

By Ed Sperling - 27 Sep, 2021 - Comments: 0

Some circuits are always on. A smart phone wakes up when it senses a user, and a smart speaker responds to keywords. The challenge is to make sure these devices don’t consume a lot of power while the rest of a device is powered down, that it remains secure, and that it can quickly wake up whatever other functions are needed. All of this requires a significant amount of engineering work. Amol ... » read more

Power-Aware Test: Addressing Power Challenges In DFT And Test

By Rahul Singhal - 10 Aug, 2021 - Comments: 0

Integrated circuit (IC) sizes continue to grow as they meet the compute requirements of cutting-edge applications such as artificial intelligence (AI), autonomous driving, and data centers. As design sizes increase, the total power consumption of the chip also increases. While process node scaling reduces a transistor’s size and its operating-voltage, power scaling has not kept up with the si... » read more

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success

By Harry Foster - 08 Jul, 2021 - Comments: 0

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification trends in IC/ASIC language and library adoption, low power management, and verification effectiveness. We then take a deeper dive into two somewhat surprising phenomena revealed in the data: the ... » read more

Tapping Into Non-Volatile Logic

By Bryon Moyer - 21 Apr, 2021 - Comments: 0

Research is underway to develop a new type of logic device, called non-volatile logic (NVL), based on ferroelectric FETs. FeFETs have been a topic of high interest at recent industry conferences, but the overwhelming focus has been using them in memory arrays. The memory bit cell, however, is simply a transistor that can store a state. That can be leveraged in other applications. “Non-v... » read more

SoC Integration Complexity: Size Doesn’t (Always) Matter

By Kurt Shuler - 01 Apr, 2021 - Comments: 2

It’s common when talking about complexity in systems-on-chip (SoCs) to haul out monster examples: application processors, giant AI chips, and the like. Breaking with that tradition, consider an internet of things (IoT) design, which can still challenge engineers with plenty of complexity in architecture and integration. This complexity springs from two drivers: very low power consumption, eve... » read more

Domain-Specific Memory

By Brian Bailey - 11 Mar, 2021 - Comments: 2

Domain-specific computing may be all the rage, but it is avoiding the real problem. The bigger concern is the memories that throttle processor performance, consume more power, and take up the most chip area. Memories need to break free from the rigid structures preferred by existing software. When algorithms and memory are designed together, improvements in performance are significant and pr... » read more

An Integrated Approach To Power Domain And CDC Verification

By Kurt Takara - 11 Mar, 2021 - Comments: 0

Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power... » read more

Timing Challenges In The Age Of AI Hardware

By Quiyang Wu - 25 Feb, 2021 - Comments: 0

In recent years, we have seen a clear market trend towards dedicated integrated circuits (ASICs) that are much more efficient in performance and energy consumption than traditional general-purpose computers for processing AI workloads. These AI accelerators harden deep learning algorithm kernels into circuits, enable higher data ingestion bandwidth with local memory, and perform massively paral... » read more

Design Support For A Green IoT

By Dirk Mayer - 11 Feb, 2021 - Comments: 0

By Dirk Mayer and Roland Jancke The Internet of Things (IoT) is growing rapidly all around the world. New devices are continually being added, all collecting a variety of data and transmitting them (often wirelessly) to edge devices, which in turn relay the data to the cloud for further processing. It is estimated that in a few years IoT devices will be responsible for over 20% of global ene... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: low power