The Murky World Of AI Benchmarks


AI startup companies have been emerging at breakneck speed for the past few years, all the while touting TOPS benchmark data. But what does it really mean and does a TOPS number apply across every application? Answer: It depends on a variety of factors. Historically, every class of design has used some kind of standard benchmark for both product development and positioning. For example, SPEC... » read more

Capturing Bugs Visually


This paper presents a new way to comprehend complex scenarios, in order to significantly accelerate bug detection and resolution. By defining a new visual language, which creates interaction vertices between the simulation scenarios and the code structure on a single matrix, we offer a novel way to compare multiple cycles. It enables verification engineers to reach solid conclusions regarding a... » read more

Using Big Data For Yield And Reliability


John O’Donnell, CEO of yieldHUB, talks about the importance of clean data for traceability, yield improvement and device reliability, where and how it gets cleaned, and why that needs to be accompanied by domain expertise. » read more

What’s Next With AI In Fabs?


Semiconductor Engineering sat down to discuss the issues and challenges with machine learning in semiconductor manufacturing with Kurt Ronse, director of the advanced lithography program at Imec; Yudong Hao, senior director of marketing at Onto Innovation; Romain Roux, data scientist at Mycronic; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. Part one ... » read more

Manufacturing Bits: April 21


Memristors reappear The University of Massachusetts Amherst has taken a step towards of the realization of neuromorphic computing--it has devised bio-voltage memristors based on protein nanowires. In neuromorphic computing, the idea is to bring the memory closer to the processing tasks to speed up a system. For this, the industry is attempting to replicate the brain in silicon. The goal is ... » read more

Designing Ultra Low Power AI Processors


AI chip design is beginning to shift direction as more computing moves to the edge, adding a level of sophistication and functionality that typically was relegated to the cloud, but in a power envelope compatible with a battery. These changes leverage many existing tools, techniques and best practices for chip design. But they also are beginning to incorporate a variety of new approaches tha... » read more

What Is DRAM’s Future?


Memory — and DRAM in particular — has moved into the spotlight as it finds itself in the critical path to greater system performance. This isn't the first time DRAM has been the center of attention involving performance. The problem is that not everything progresses at the same rate, creating serial bottlenecks in everything from processor performance to transistor design, and even the t... » read more

AI Requires Tailored DRAM Solutions


For over 30 years, DRAM has continuously adapted to the needs of each new wave of hardware spanning PCs, game consoles, mobile phones and cloud servers. Each generation of hardware required DRAM to hit new benchmarks in bandwidth, latency, power or capacity. Looking ahead, the 2020s will be the decade of artificial intelligence/machine learning (AI/ML) touching every industry and applicatio... » read more

New Ways To Optimize Machine Learning


As more designers employ machine learning (ML) in their systems, they’re moving from simply getting the application to work to optimizing the power and performance of their implementations. Some techniques are available today. Others will take time to percolate through the design flow and tools before they become readily available to mainstream designers. Any new technology follows a basic... » read more

More Multiply-Accumulate Operations Everywhere


Geoff Tate, CEO of Flex Logix, sat down with Semiconductor Engineering to talk about how to build programmable edge inferencing chips, embedded FPGAs, where the markets are developing for both, and how the picture will change over the next few years. SE: What do you have to think about when you're designing a programmable inferencing chip? Tate: With a traditional FPGA architecture you ha... » read more

← Older posts Newer posts →