Tech Talk: Multipatterning, Take Two

By Brian Bailey - 31 Mar, 2014 - Comments: 0

Mentor Graphics' David Abercrombie continues with his whiteboard talk about coloring with advanced lithography, including what goes wrong and how to fix it. [youtube vid=HCBtvHCcbf4] » read more

Impact Of Illumination On Model-Based SRAF Placement For Contact Patterning

By Various Writers - 19 Feb, 2014 - Comments: 1

Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and for random log... » read more

What’s The Backup Plan?

By Ed Sperling - 23 Jan, 2014 - Comments: 0

Over the past dozen years we have witnessed two major breakdowns in the global semiconductor supply chain. The first occurred in 2002, when an outbreak of severe acute respiratory syndrome (SARS) basically closed off Chinese manufacturing for several months. The second major problem occurred in 2011, when the Tohoku earthquake and a devastating tsunami shut down a good portion of Japanese produ... » read more

The Next Big Threat: Manufacturing

By Ed Sperling - 23 Jan, 2014 - Comments: 0

The business adage that you’re only as good as your partners should be a core principle of doing business when it comes to security. But with a complex SoC you don’t always know all your partners, who financed them—or worse, who else they’re working with or working for. Consider this scenario: A band of sophisticated thieves grinds off the top of an SoC package, inserts probes to map... » read more

Experts At The Table: MEMS Challenges

By Mark LaPedus - 20 Dec, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the challenges of MEMS with Rakesh Kumar, senior director of the MEMS program at GlobalFoundries; Tak Tanaka, managing director for Applied Global Services at Applied Materials; Paul Lindner, executive technology director at EV Group; and Alissa M. Fitzgerald, founder and managing member at A.M. Fitzgerald & Associates. What follows are excerpts... » read more

New Pain And Inflection Points

By Ed Sperling - 24 Oct, 2013 - Comments: 0

Jack Harding, CEO of eSilicon, talks with Semiconductor Engineering about the explosion in the costs and the risk of semiconductor designs at the leading edge of Moore's Law. [youtube vid=HLS5QhnGHfM] » read more

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP

By Various Writers - 17 Jul, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~ ~ According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30% increase in performance over 28nm bulk LPS PolySiON, HPP increases die ... » read more

Foundry Talk

By Ed Sperling - 07 Jul, 2013 - Comments: 0

GlobalFoundries CEO Ajit Manocha sounds off on Foundry 2.0, 450mm wafers, lithography challenges, stacked die, the Internet of Things and the rush to the next process node. [youtube vid=WfjtlZkCi0w] » read more

Let’s All Meet At The Via Bar!

By Jean-Marie Brunet - 30 Jun, 2013 - Comments: 0

By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

Extending Copper Interconnect Beyond The 14nm Node

By Various Writers - 20 Jun, 2013 - Comments: 0

Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing. To find out more about what's changing in this area and why it's so important, click here. » read more

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tag: manufacturing

Tech Talk: Multipatterning, Take Two

Impact Of Illumination On Model-Based SRAF Placement For Contact Patterning

What’s The Backup Plan?

The Next Big Threat: Manufacturing

Experts At The Table: MEMS Challenges

New Pain And Inflection Points

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP

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Let’s All Meet At The Via Bar!

Extending Copper Interconnect Beyond The 14nm Node

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