tag: Mentor Graphics

Formal Verification Comes Of Age
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler Formal verification technology, also known as formal property checking, has been in existence since the early 1990s. Still, it’s only in the past five years that it has made big strides in the last five years in terms of the capacity of the technology to handle bigger pieces of a design, leveraging advancements in computing as well as improvements to the algor... » read more

The X Factor
By Ed Sperling - 30 May, 2013 - Comments: 0

By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market windows. Tools are available to deal with some of these unknowns, or X’s, but certainly not all of them. Moreover, no single tool can handle all unknowns, some of which can build upon other unkn... » read more

Experience Required
By The SE Staff - 30 May, 2013 - Comments: 0

Many prominent semiconductor, EDA and IP companies are acknowledging the influence of user-experience design methodologies and technologies on their business. Experiences are the evolution of commoditization (chip hardware) and customization (software). But many design engineers remain cautious about the actual application of experiences to their work. What is driving this emphasis on expe... » read more

Development of Complex Multicore Systems: Tracing Challenges and Concept
By Various Writers - 30 May, 2013 - Comments: 0

This white paper is the first paper of a two-part Mentor Embedded multicore white paper series. In this paper, the challenges software developers face when developing, debugging, and validating software applications for a complex multicore system will be discussed. The paper also highlights some of the questions around hardware resource usage, tracing aids, tracing domains, and concepts for col... » read more

DFM Success At SMIC
By Mentor, a Siemens Business - 28 May, 2013 - Comments: 0

Jeff Wilson As any integrated circuit (IC) designer knows, design rules are the “first line of defense” foundries provide in the effort to ensure all IC designs are ultimately manufacturable. Coming in a close second, design for manufacturing (DFM) rules enable designers to maximize design capabilities and performance while minimizing or optimizing the use of chip space. At today’s ad... » read more

3D Brings Test Into Fashion
By Ann Mutschler - 16 May, 2013 - Comments: 0

By Ann Steffora Mutschler As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to... » read more

Between A Rock And A Hard Place
By David Abercrombie - 16 May, 2013 - Comments: 0

By David Abercrombie My previous articles included a lot of discussion about correcting error violations in double patterning (DP). This time let’s take a step back up the design flow. DP requires a design team to make some important decisions about standard cell design methodologies, or risk running into serious placement issues down the line. Understanding why this is so, and what your opt... » read more

EUV Flare And Proximity Modeling And Model-Based Correction
By Various Writers - 16 May, 2013 - Comments: 0

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in seve... » read more

BIST For Low-Power Devices
By Steve Pateras - 09 May, 2013 - Comments: 0

By Stephen Pateras The persistent growth of mobile computing is driving an increasing need to manage power consumption within semiconductor devices. This has significant implications on the design and test of these devices. Low-power requirements affect test in two separate ways. First, it’s important to ensure that any functional power constraints are met (or at least adequately managed) du... » read more

Roundtable: Is The Chip Ready
By Ed Sperling - 09 May, 2013 - Comments: 0

Mobile devices demand complex chips—so complex to build that signoff has become something of a balancing act between what the verification teams believe is good enough and time-to market demands. Low-Power/High-Performance Engineering talked about this with Simbal Rafiq, director of engineering at Applied Micro; Robert Hoogenstryd, senior director of marketing for design analysis and signoff ... » read more

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