tag: Mentor Graphics

20nm IP Portability Appears Virtually Impossible
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a ... » read more

More Intelligent Verification
By Jon McDonald - 22 Sep, 2011 - Comments: 0

By Jon McDonald If I have flipped a coin 1,000 times and it's come up heads every time what are the odds that I will get another head on the next flip? The odds on the next flip are still 50/50. The fact that I observe a uniquely unlikely situation has no impact on my current probability, and frankly any sequence of prior results would be equally unlikely. I find some of the same thinking appl... » read more

DFT: Essential For Power-Aware Test
By Ed Sperling - 18 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

Multi-Patterning: Game Changer or Y2K?
By Mentor Graphics Staff Writers - 14 Sep, 2011 - Comments: 0

By Joe Davis, Mentor Graphics Every new technology node brings new process challenges that translate into design challenges. For the last five years, design rules and processes have had to deal with an increasing impact from nearest-neighbor and environmental effects from lithography, stress, and temperature. Where once cells could be designed and placed independently, now a cell’s real pe... » read more

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

Interconnect Power II
By Barry Pangrle - 08 Sep, 2011 - Comments: 0

Barry Pangrle After submitting last month’s blog, I read a very interesting article by Deepak Sekar analyzing Intel’s 22 nm FinFET technology versus a hypothetical planar 22nm CMOS technology. Beyond the advantages of being able to use a 140 mV reduction in the supply voltage for the trigate technology, Deepak did a breakdown analysis for the predicted power across a representative micropr... » read more

Support the Arts! in Custom Design Verification
By Mentor Graphics Staff Writers - 01 Sep, 2011 - Comments: 0

By Joe Davis Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these ICs is also increasing, reflecting strong growth in wireless technologies such as WiFi, Bluetooth, 3G, and 4G, as well as GPS, audio, imaging, and sensor technologies. Market research indicates that while analog circuitry occupies only 20% of the ar... » read more

Testing One, Two, Three
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ed Sperling The rule of thumb at 90nm—still one of the mainstream process nodes—has been that test is something you do when a chip is done. You attach electrodes on either side, make sure the signal comes through clearly, and that the SoC functions properly. Try the same thing at 40nm, with multiple power islands, multiple voltage rails, lots of third-party IP and usually a slew of p... » read more

Which Came First?
By Jon McDonald - 25 Aug, 2011 - Comments: 0

By Jon McDonald Which came first the chicken or the egg? Based on some of my recent discussions I could ask the question in a slightly different way: “Which came first, the hardware or the software?” Depending on your point of view and personal bias the answer may appear obvious, but from what I've seen it can be very dependent on your current engineering situation. Adopting one perspectiv... » read more

Interconnect Power
By Barry Pangrle - 11 Aug, 2011 - Comments: 0

By Barry Pangrle Applied Materials announced its latest version of nano-porous low-k dielectric technology called Black Diamond 3 last month at Semicon West. What really caught my ear though was the marketing claim that 1/3 of total chip power consumption (really energy) is in the interconnect. I thought about this a bit, and certainly for some designs this seemed to easily be quite po... » read more

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