tag: Mentor Graphics

Tortuga Logic: Hardware Security
By Ed Sperling - 26 May, 2015 - Comments: 0

For the Internet of Things to really get rolling, it has to be bulletproof. And given the number of very high-profile security breaches in recent months, it has a long way to go before consumers or businesses will feel comfortable using any of a new wave of smart devices That concern has prompted a wave of acquisitions from companies such as Intel (McAffee), Cadence (Jasper Design Automation... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 22 May, 2015 - Comments: 0

At an event, Samsung rolled out its 10nm finFET technology. The company also showed a 300mm wafer with 10nm finFET transistors. "We have silicon-based PDKs out," said Kelvin Low, senior director of foundry marketing for Samsung. Samsung plans to move into production with its 10nm finFET technology by the end of 2016, he said. IC Insights released its chip rankings in terms of sales in the fi... » read more

The Week In Review: Design/IoT
By Jesse Allen - 22 May, 2015 - Comments: 0

Tools Cadence updated its Allegro PCB product line with a new manufacturing option that accelerates manufacturing documentation and technology updates for increased efficiency, control and productivity for designers and streamlining handoff to manufacturing. The release also allows users to develop custom fabrication and assembly rules. Invionics expanded its Invio EDA development platfor... » read more

How Hard Is FD-SOI Design?
By Ann Mutschler - 21 May, 2015 - Comments: 0

Fully-depleted silicon-on-insulator ([getkc id="220" kc_name="FD-SOI"]) manufacturing technology reached of point of readiness for mass production at the end of March. Along with that, it’s now clear that while there are some impacts on the design flow, those impacts are not game changers. For one thing, the tools required are the same ones currently used for 28nm planar bulk CMOS. The onl... » read more

Next-Generation Parasitic Extraction For 16nm And Beyond
By Mentor, a Siemens Business - 21 May, 2015 - Comments: 0

Advanced nodes and innovative process features such as finFET transistors require a leap forward in the performance and accuracy of analysis tools. The new Calibre xACT solution is a high-performance, high-accuracy parasitic extraction tool architected from the top-down for diverse IC design styles at advanced nodes. The Calibre xACT product delivers reference-level accuracy for leading-edge fi... » read more

Automated Chip Polishing Can Make Your Design Shine
By Bill Graupp - 21 May, 2015 - Comments: 1

Today’s modern chip design is a collaboration among many design teams, often using different design flows and different EDA tools. This state of the chip design industry can create high risk in the layout process, forcing delays in product release. To help reduce this risk, many levels of verification throughout the design flow exist to identify problematic areas in a design. While new EDA to... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2015 - Comments: 0

FinFETs change the equation for power optimization, says Mentor's Vincent Lebars – and while companies are attacking some power gains, there is much more to be had doing datapath optimization within the place and route flow. Cadence's Richard Goering talks with Oz Levia about the future direction of formal and its integration into other product lines now that the merger between Cadence and... » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 18 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Week 49: Are We There Yet?
By Anne Cirkel - 15 May, 2015 - Comments: 0

When I was a little kid my parents would pack me and my sister into the car and drive to the Mediterranean for our summer camping vacation. It was quite a haul from our home on the west side of Germany near the border with Belgium to the south of France, and as is true of any long car trip, the last stretch was the hardest. After hours in the backseat, my sister and I would be craning our necks... » read more

Rethinking Power
By Ed Sperling - 14 May, 2015 - Comments: 0

Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

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