tag: Mentor

Continuous Education For Engineers
By Brian Bailey - 29 Jul, 2021 - Comments: 0

Continuous education is essential for engineers, but many companies don't recognize the value or they are unwilling to provide the necessary resources. This should be a line of questioning before every new hire makes the decision about where they want to work, because it not only affects their future career, but also impacts the value they can provide to that company during the course of the... » read more

Tape Out On Time With Demand Signoff DRC In P&R
By Siemens EDA - 28 Jul, 2021 - Comments: 0

Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

Blog Review: July 28
By Jesse Allen - 28 Jul, 2021 - Comments: 0

Synopsys' Chris Clark considers potential vulnerabilities in automotive over-the-air updates and best practices and new standards the industry can implement to improve security of vehicle software updates. Cadence's Paul McLellan gets a look at expected new fab construction in the coming years and where capacity is being focused. Siemens' Robin Bornoff dives into electromagnetic simulatio... » read more

Blog Review: July 21
By Jesse Allen - 21 Jul, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 16 Jul, 2021 - Comments: 0

Security A new security annotation standard for hardware IP is now available for download at no cost. The board of directors of the Accellera Systems Initiative, the non-profit EDA- and IP-standards organization, approved the release of the Security Annotation for Electronic Design Integration (SA-EDI) Standard 1.0. The standard, developed by Accellera’s IP Security Assurance (IPSA) Working ... » read more

Design For Test Data
By Ed Sperling - 14 Jul, 2021 - Comments: 0

As design pushes deeper into data-driven architectures, so does test. Geir Eide, director for product management of DFT and Tessent Silicon Lifecycle Solutions at Siemens Digital Industries Software, talks with Semiconductor Engineering about a subtle but significant shift for designing testability into chips so that test data can be used at multiple stages during a device’s lifetime. » read more

Blog Review: July 14
By Jesse Allen - 14 Jul, 2021 - Comments: 0

Siemens EDA's Wei-Lii Tan considers the tradeoffs when running library characterization in the cloud and how to think about running CPUs in parallel, the cost of throughput, and runtime reductions. A Synopsys writer checks out the reduced blanking feature in HDMI 2.1, which can help reduce the transmission rate while keeping the resolution and refresh rate intact for higher resolution displa... » read more

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets
By Ed Sperling - 14 Jul, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; an... » read more

Streaming Scan Network
By Siemens EDA - 12 Jul, 2021 - Comments: 0

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. In the traditional approach to delivering scan test data to cores, each core requires a dedicated connection to chip-level pins, which doesn’t allow for much flexibility, as the dependencies betwee... » read more

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success
By Harry Foster - 08 Jul, 2021 - Comments: 0

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification trends in IC/ASIC language and library adoption, low power management, and verification effectiveness. We then take a deeper dive into two somewhat surprising phenomena revealed in the data: the ... » read more

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