Chip Design Shifts As Fundamental Laws Run Out Of Steam

By Ann Mutschler - 31 Oct, 2022 - Comments: 12

Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

Week In Review: Semiconductor Manufacturing, Test

By Karen Heyman - 28 Oct, 2022 - Comments: 0

This week saw more fallout from U.S. export controls: SK hynix may consider selling its memory chip production facilities in China if recently imposed controls make it too difficult to continue operations there, according to Nikkei Asia. "As a contingency plan, we are considering selling the fab, selling the equipment or transferring the equipment to South Korea," said Kevin Noh, SK hynix ... » read more

Week In Review: Design, Low Power

By Marie C. Baca - 28 Oct, 2022 - Comments: 0

Tools and IP Scandinavian researchers used a laser-powered chip to transmit about 1.84 petabytes of data over a fiber optic cable in one second. The scientists said the technology could lead to faster broadband speeds and reduce the amount of energy used to keep the internet running. Imec said the semiconductor industry is likely to see increasing separation of power delivery and signal rou... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 28 Oct, 2022 - Comments: 0

Automotive, mobility Ford Motor Company revealed it lost $827 million in the third quarter because of parts shortages and unexpected supplier costs. Those shortages affected 40,000 to 50,000 vehicles. The company is shutting down its interest in its self-driving car unit Argo.ai, which it shared with Volkswagen since 2019. Ford will instead focus on advanced driver-assist systems (ADAS), which... » read more

Raising IP Integration Up A Level

By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Considering The Power Of The Cloud For EDA

By Michael White - 27 Oct, 2022 - Comments: 0

By Michael White, Siemens EDA, in technical collaboration with Peeyush Tugnawat, Google Cloud, and Philip Steinke, AMD At DAC 2022, Google Cloud, AMD, and Calibre Design Solutions presented an EDA in the cloud solution that enables companies to access virtually unlimited compute resources when and as needed to optimize their design and verification flows. If your company is considering addin... » read more

Addressing SRAM Verification Challenges

By Siemens EDA - 26 Oct, 2022 - Comments: 0

SureCore Limited is an SRAM IP company based in Sheffield, the United Kingdom, that develops low power memories for current and next generation silicon process technologies. Its award-winning, world-leading, low power SRAM designs are process independent and variability tolerant, making them suitable for a wide range of technology nodes. Two major product families have been announced: PowerM... » read more

Blog Review: Oct. 26

By Jesse Allen - 26 Oct, 2022 - Comments: 0

Synopsys' Teng-Kiat Lee and Sandeep Mehndiratta argue that IC design in the cloud can support an existing on-prem strategy, enable large and small enterprises to manage cost and capacity more effectively, and offer security for valuable semiconductor IP. Siemens EDA's Chris Spear finds that SystemVerilog classes are a good way to encapsulate both variables and the routines that operates on t... » read more

Testing 2.5D And 3D-ICs

By Ed Sperling - 25 Oct, 2022 - Comments: 0

Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the ... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 21 Oct, 2022 - Comments: 0

Automotive, mobility The BMW Group will invest $1.7 billion in its U.S. operations to build electric vehicles and batteries, mostly in South Carolina. BMW will drop $1 billion in its South Carolina plant for EV production and $700 million for a new battery-assembly facility in the state. BMW also agreed to purchase battery cells from Japan-based Envision AESC, which plans to construct a new ba... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: Mentor

Chip Design Shifts As Fundamental Laws Run Out Of Steam

Week In Review: Semiconductor Manufacturing, Test

Week In Review: Design, Low Power

Week In Review: Auto, Security, Pervasive Computing

Raising IP Integration Up A Level

Considering The Power Of The Cloud For EDA

Addressing SRAM Verification Challenges

Blog Review: Oct. 26

Testing 2.5D And 3D-ICs

Week In Review: Auto, Security, Pervasive Computing