Automation of Sample Plan Creation For Process Model Calibration

By Various Writers - 17 Jul, 2013 - Comments: 0

The process of preparing a sample plan for optical and resist model calibration has always been tedious. Not only because it is required to accurately represent full chip designs with countless combinations of widths, spaces and environments, but also because of the constraints imposed by metrology which may result in limiting the number of structures to be measured. Also, there are other limit... » read more

Seeing Spots At 10nm

By Ed Sperling - 15 Jul, 2013 - Comments: 0

By Ed Sperling The relentless march to smaller process nodes means the defects are getting smaller, more numerous, and much harder to find. That explains why Applied Materials and KLA-Tencor both introduced new defect review and classification tools last week. The move to the 1x nm is on the top of both companies’ agendas, and with that comes defects on the walls of finFETs in addition to... » read more

Experts At The Table: Issues In Metrology And Inspection

By Mark LaPedus - 06 May, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss future metrology and inspection challenges with John Allgair, senior member of the technical staff at GlobalFoundries; Kevin Heidrich, vice president of marketing and business development at Nanometrics; Robert Newcomb, executive vice president at Qcept Technologies; and Shrinivas Shetty, vice president of marketing f... » read more

Waiting For 3D Metrology

By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear. 3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die ... » read more

Experts At The Table: Issues In Metrology And Inspection

By Mark LaPedus - 18 Apr, 2013 - Comments: 0

Wanted: New Metrology Funding Models

By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing. Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology. ... » read more

Swimming In Data

By Ed Sperling - 21 Mar, 2013 - Comments: 0

By Ed Sperling So many warnings about data overload have been issued over the past decade that people generally have stopped paying attention to them. The numbers are so astronomical that increases tend to lose meaning. Nowhere is this more evident than in the semiconductor metrology world, where files are measured in gigabytes. And at each new process node, as the number of transistors a... » read more

New Math

By Ed Sperling - 18 Oct, 2012 - Comments: 0

It was nice when we had round numbers to work with. It was pretty simple to move from 180nm to 120nm and then to 90nm. Then the half nodes started—45/40, 32/28 and 22/20nm. After 14nm we are poised dangerously over the single-digit process nodes. Intel is working on 10nm, to be followed by 7nm or 5nm. Other companies are looking at 11nm, to be followed by 8nm, 6nm or something even further... » read more

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Knowledge Centers
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tag: metrology

Automation of Sample Plan Creation For Process Model Calibration

Seeing Spots At 10nm

Experts At The Table: Issues In Metrology And Inspection

Waiting For 3D Metrology

Experts At The Table: Issues In Metrology And Inspection

Wanted: New Metrology Funding Models

Swimming In Data

New Math