A Photonic Circuit Architecture Allowing Faster, More Efficient Transfer of Large Amounts of Data


A technical paper titled "Massively scalable Kerr comb-driven silicon photonic link" was published by researchers at Columbia University and Air Force Research Laboratory. Abstract: "The growth of computing needs for artificial intelligence and machine learning is critically challenging data communications in today’s data-centre systems. Data movement, dominated by energy costs and limi... » read more

Balancing AI And Engineering Expertise In The Fab


Modeling and simulation are playing increasingly critical roles in chip development due to tighter process specs, shrinking process windows, and fierce competition to bring technologies to market first. Before a new device makes it to high-volume manufacturing, there are countless engineering hours spent on developing the lithography, etching, deposition, CMP, and many other processes, at hi... » read more

Object Detection CNN Suitable For Edge Processors With Limited Memory


A technical paper titled “TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers” was published by researchers at ETH Zurich. Abstract: "This paper introduces a highly flexible, quantized, memory-efficient, and ultra-lightweight object detection network, called TinyissimoYOLO. It aims to enable object detection on microcontrol... » read more

Welcome To EDA 4.0 And The AI-Driven Revolution


By Dan Yu, Harry Foster, and Tom Fitzpatrick Welcome to the era of EDA 4.0, where we are witnessing a revolutionary transformation in electronic design automation driven by the power of artificial intelligence. The history of EDA can be delineated into distinct periods marked by significant technological advancements that have propelled faster design iterations, improved productivity, and fu... » read more

RL-Guided Detailed Routing Framework for Advanced Custom Circuits


A technical paper titled "Reinforcement Learning Guided Detailed Routing for Custom Circuits" was published by researchers at UT Austin, Princeton University, and NVIDIA. "This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. C... » read more

Managing Water Supplies With Machine Learning


From wet benches to cooling systems, fabs use vast amounts of water — millions of gallons per day at a typical foundry. In this era of climate change, though, water supplies are becoming less reliable and municipal water systems are becoming more restrictive. For example, local utilities might restrict a fab’s ability to draw from the public water supply, or might supply only treated wastew... » read more

Machine Vision Plus AI/ML Adds Vast New Opportunities


Traditional technology companies and startups are racing to combine machine vision with AI/ML, enabling it to "see" far more than just pixel data from sensors, and opening up new opportunities across a wide swath of applications. In recent years, startups have been able to raise billions of dollars as new MV ideas come to light in markets ranging from transportation and manufacturing to heal... » read more

GDDR6 Delivers The Performance For AI/ML Inference


AI/ML is evolving at a lightning pace. Not a week goes by right now without some new and exciting developments in the field, and applications like ChatGPT have brought generative AI capabilities firmly to the forefront of public attention. AI/ML is really two applications: training and inference. Each relies on memory performance, and each has a unique set of requirements that drive the choi... » read more

Making Tradeoffs With AI/ML/DL


Machine learning, deep learning, and AI increasingly are being used in chip design, and they are being used to design chips that are optimized for ML/DL/AI. The challenge is understanding the tradeoffs on both sides, both of which are becoming increasingly complex and intertwined. On the design side, machine learning has been viewed as just another tool in the design team's toolbox. That's s... » read more

Optimizing Scan Test For Complex ICs


As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability. In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifec... » read more

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