What Are EDA’s Big Three Thinking?

By Ed Sperling - 24 Apr, 2014 - Comments: 4

Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult... » read more

Improving Yield Of 2.5D Designs

By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

Tech Talk: Multipatterning, Take Two

By Brian Bailey - 31 Mar, 2014 - Comments: 0

Mentor Graphics' David Abercrombie continues with his whiteboard talk about coloring with advanced lithography, including what goes wrong and how to fix it. [youtube vid=HCBtvHCcbf4] » read more

EUV Reaches A Crossroads

By Mark LaPedus - 20 Mar, 2014 - Comments: 3

[gettech id="31045" comment="EUV"] (EUV) [getkc id="80" comment="lithography"] is at a crossroads. 2014 represents a critical year for the technology. In fact, it may answer a pressing question about EUV: Does it work or not? It’s too early to make that determination right now, but there are more uncertainties than ever for the oft-delayed technology. Originally aimed for the 65nm node in... » read more

Advanced Lithography: Moore’s Law Moves On

By Marc David Levenson - 20 Mar, 2014 - Comments: 1

Every February, experts in nano patterning technologies converge in San Jose, Calif., to present their road maps, brainstorms and results at the SPIE Advanced Lithography Symposium. This year, there was more confusion than ever, partly the result of sessions in unlabeled (but beautiful) new ballrooms at the Convention Center, but mostly because of industry divergences. There is no longer a s... » read more

Tech Talk: Multipatterning

By Brian Bailey - 03 Mar, 2014 - Comments: 2

Mentor Graphics' David Abercrombie shows how multi patterning is supposed to be done, and what sorts of problems can crop up along the way. Now that EUV has hit another hiccup, the semiconductor industry has little choice. [youtube vid=tOs_OMSh4Nk] » read more

Why does EUV matter?

By Brian Bailey - 01 Oct, 2013 - Comments: 0

By Brian Bailey The end of Moore’s Law has been predicted for almost as long as the law has existed. It normally comes down to some great technological barrier that cannot be breached, only to find that a solution is just around the corner and the concerns fade until the next barrier is identified. At DAC this year (2013), there were many predictions about why Moore’s Law will end in th... » read more

Reaching For The Reset Button In Lithography

By Mark LaPedus - 21 Mar, 2013 - Comments: 0

By Mark LaPedus Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning. Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition... » read more

Facing Up To RC Delay

By Ed Sperling - 15 Nov, 2012 - Comments: 0

y Ed Sperling Resistance and capacitance delays have always been someone else’s problem to solve at some fuzzy process node in the future, and for the most part manufacturers and equipment makers have done a wizard-like job of making this problem go away. They can’t make it disappear anymore, though, and beginning at 14nm and beyond RC delay is becoming more than just an annoyance. The ... » read more

Beam Me Up

By Ed Sperling - 18 Oct, 2012 - Comments: 0

By Mark LaPedus For years, electron-beam tools have been struggling to keep up with photomask complexity, causing an alarming increase in write times and mask production costs. Intel and others recently warned that e-beams soon could reach their fundamental limits, thereby requiring the need for new solutions. And in the multiple patterning era, mask makers could see their capital costs soa... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?