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Future Directions Unknown


The semiconductor industry has been on cruise control when it comes to shrinking features, but as process technology progresses to 10nm and 7nm there will be some significant changes. For one thing, the cost per new design will continue to rise, which means only the largest companies with the biggest market opportunity will be able to invest at the leading-edge nodes. Chips for mobile phones... » read more

Is Multi-Patterning Good for You?


I think we can all remember growing up and our parents making us take nasty-tasting medicines, or eat foods we didn’t like, or endure painful things like shots, all under the banner of “It is good for you!” We didn’t like it then, and we still don’t like it as adults. We would all prefer a way to lose weight while eating anything we want, or building strong muscles and aerobic health ... » read more

Signoff Intensity On The Rise


By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

Improving 2.5D Components


A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

IP And FinFETs At Advanced Nodes


Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation. SE: What happens with the next revs of finFET... » read more

DFM And Multipatterning


Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

DFM And Multipatterning


Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

Blog Review: July 2


Mentor’s Nazita Saye has reservations about driverless cars. Sometimes it’s actually fun to drive—and sometimes it isn’t. Cadence’s Brian Fuller is a bit more optimistic about driverless cars. He says that from the standpoint of safety, efficiency and environment, autonomous vehicles will be a big step forward—if and when some critical problems are solved. And along the same... » read more

How Much Multipatterning?


The latest consensus among litho experts is that extreme ultraviolet (EUV) will appear in the market sometime in coming months in a commercially viable form. The only question is the degree of commercially viability, and what it will actually cost. While some debate lingers about whether EUV will ever get going, the general feeling is that enough progress has been made recently to make it work.... » read more

What Are EDA’s Big Three Thinking?


Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult... » read more

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