Shortening Network-on-Chip Development Schedules Using Physical Awareness

By Frank Schirrmeister - 05 Jan, 2023 - Comments: 0

Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp uptick in concerns about whether a design that may be functionally correct can also be implemented using physical implementation flows. Given the intricacies and complexity of network-on-chip (NoC... » read more

When Does My SoC Design Need A NoC?

By Michael Frank - 01 Dec, 2022 - Comments: 0

By Michael Frank and Frank Schirrmeister Excluding the simplest offerings, almost every modern system-on-chip (SoC) device will implement its on-chip communications utilizing a network-on-chip (NoC). Some people question whether it is necessary to use a NoC or whether a more basic approach would suffice. What is in an SoC? An SoC is an integrated circuit (IC) that incorporates most or all ... » read more

Fast and Flexible FPGA-based NoC Hybrid Emulation

By Technical Paper Link - 14 Jul, 2022 - Comments: 0

Researchers from RWTH Aachen University and Otto-von-Guericke Universitat Magdeburg have published a new technical paper titled "EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs." Abstract: "Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling co... » read more

TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms

By Technical Paper Link - 04 Jul, 2022 - Comments: 0

New technical paper titled "AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors" from researchers at Technische Universitaet Dresden (TU Dresden). Partial Abstract: "In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heter... » read more

A New Breed Of EDA Required

By Brian Bailey - 23 Jun, 2022 - Comments: 1

While doing research for one of my stories this month, a couple of people basically said that applying methodologies of the past to the designs of today can be problematic because there are fundamental differences in the architectures and workloads. While I completely agree, I don't think these statements go far enough. Designs of today generally have one of everything — one CPU, one accel... » read more

OTA On-Chip Computing That Conquers A Bottleneck In Wired NoC Architectures

By Technical Paper Link - 21 Jun, 2022 - Comments: 0

New research paper titled "Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing" from researchers at IBM Research, Zurich Switzerland and Universitat Politecnica de Catalunya, Barcelona, Spain Abstract: "Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hyp... » read more

Deep Reinforcement Learning to Dynamically Configure NoC Resources

By Technical Paper Link - 17 Jun, 2022 - Comments: 0

New research paper titled "Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energy-Efficient Computing Systems" from Md Farhadur Reza at Eastern Illinois University. Find the open access technical paper here. Published June 2022. M. F. Reza, "Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energ... » read more

Optimizing NoC-Based Designs

By Paul Graykowski - 05 May, 2022 - Comments: 0

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are re... » read more

AI-Based Method to Prune the Design Space of Heterogeneous NoCs

By Technical Paper Link - 02 May, 2022 - Comments: 0

Abstract "Often suffering from under-optimization, Networks-on-Chip (NoCs) heavily impact the efficiency of domain-specific Systems-on-Chip. To cope with this issue, heterogeneous NoCs are promising alternatives. Nevertheless, the design of optimized NoCs satisfying multiple performance objectives is extremely challenging and requires significant expertise. Prior works failed to combine many... » read more

Data Security Challenges In Automotive

By Ann Mutschler - 03 Feb, 2022 - Comments: 1

Automakers are scrambling to prevent security breaches and data hacks in new vehicles while simultaneously adding new and increasingly autonomous features into vehicles that can open the door to new vulnerabilities. These two goals are often at odds. As with security in any complex system, nothing is ever completely secure. But even getting a handle on this multilayered issue is a challenge.... » read more

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tag: network on chip

Shortening Network-on-Chip Development Schedules Using Physical Awareness

When Does My SoC Design Need A NoC?

Fast and Flexible FPGA-based NoC Hybrid Emulation

TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms

A New Breed Of EDA Required

OTA On-Chip Computing That Conquers A Bottleneck In Wired NoC Architectures

Deep Reinforcement Learning to Dynamically Configure NoC Resources

Optimizing NoC-Based Designs

AI-Based Method to Prune the Design Space of Heterogeneous NoCs

Data Security Challenges In Automotive

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