The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs

By NetSpeed Systems - 23 Mar, 2016 - Comments: 0

The last few decades have seen a massive growth in the number of CPU cores, computing clusters and other IP blocks in a SoC. This massive growth along with the need for complex chip integration has driven the need for sophisticated interconnects. SoC architects have employed a variety of methods from buses to crossbars to handcrafted NoCs with Lego-like blocks with varying degrees of success. T... » read more

Optimizing Enterprise-Class SSD Host Controller Design With Arteris FlexNoC Network-On-Chip Interconnect IP

By Arteris - 26 Feb, 2016 - Comments: 0

Solid state storage is rapidly supplanting rotary storage in data center computing, driven by the competing needs for lower power consumption, lower latency and higher bandwidth. But the inherent unreliability of flash cells mandates the use of sophisticated host controllers to guarantee data reliability and endurance for enterprise solid state disks (SSD). Leading enterprise SSD companies have... » read more

How To Reduce Timing Closure Headaches

By Kurt Shuler - 22 Dec, 2015 - Comments: 0

As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

On-Chip Networks Optimize Shared Memory For Multicore SoCs

By Sonics - 23 Nov, 2015 - Comments: 0

Performance of multicore SoCs is often dominated by external DRAM access, particularly in digital consumer devices running high quality video and graphics applications. Increasing core counts and newer DRAMs make the problems much more difficult. This article covers optimization of the on-chip network and memory system to achieve the required system throughput. For more information, click here. » read more

Top 5 Reasons The SoC Interconnect Matters

By Kurt Shuler - 29 Oct, 2015 - Comments: 0

The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

NoC Versus PIN: Size Matters

By Drew Wingard - 09 Oct, 2015 - Comments: 1

Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC archi... » read more

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations

By Randy Smith - 24 Sep, 2015 - Comments: 0

When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the G... » read more

Lightweight Cryptography For The IoE

By Ernest Worthman - 03 Sep, 2015 - Comments: 0

This is the age where technology is expected to do more, faster, anonymously, and often invisibly. And it's supposed to use less power, with smaller footprints, unobtrusively and intuitively. And all that needs to be protected with cryptography. That's the goal, at least. But as Simon Blake-Wilson, vice president of products and marketing for [getentity id="22671" e_name="Rambus"]' Cryptogra... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency

By Kurt Shuler - 27 Aug, 2015 - Comments: 0

Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

Poised For Aspect-Oriented Design?

By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

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tag: NoC

The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs

Optimizing Enterprise-Class SSD Host Controller Design With Arteris FlexNoC Network-On-Chip Interconnect IP

How To Reduce Timing Closure Headaches

On-Chip Networks Optimize Shared Memory For Multicore SoCs

Top 5 Reasons The SoC Interconnect Matters

NoC Versus PIN: Size Matters

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations

Lightweight Cryptography For The IoE

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency

Poised For Aspect-Oriented Design?

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