How To Reduce Timing Closure Headaches

By Kurt Shuler - 22 Dec, 2015 - Comments: 0

As chips have become more complex, timing closure has provided some of the most vexing challenges facing design engineers today. This step requires an increasing amount of time to complete and adds significantly to design costs and back-end schedule risks. Wire delay dominates transistor switching delay Building high-performance modern CPUs involves pipelining to achieve high frequencies. I... » read more

On-Chip Networks Optimize Shared Memory For Multicore SoCs

By Sonics - 23 Nov, 2015 - Comments: 0

Performance of multicore SoCs is often dominated by external DRAM access, particularly in digital consumer devices running high quality video and graphics applications. Increasing core counts and newer DRAMs make the problems much more difficult. This article covers optimization of the on-chip network and memory system to achieve the required system throughput. For more information, click here. » read more

Top 5 Reasons The SoC Interconnect Matters

By Kurt Shuler - 29 Oct, 2015 - Comments: 0

The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

NoC Versus PIN: Size Matters

By Drew Wingard - 09 Oct, 2015 - Comments: 1

Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC archi... » read more

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations

By Randy Smith - 24 Sep, 2015 - Comments: 0

When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the G... » read more

Lightweight Cryptography For The IoE

By Ernest Worthman - 03 Sep, 2015 - Comments: 0

This is the age where technology is expected to do more, faster, anonymously, and often invisibly. And it's supposed to use less power, with smaller footprints, unobtrusively and intuitively. And all that needs to be protected with cryptography. That's the goal, at least. But as Simon Blake-Wilson, vice president of products and marketing for [getentity id="22671" e_name="Rambus"]' Cryptogra... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency

By Kurt Shuler - 27 Aug, 2015 - Comments: 0

Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

Poised For Aspect-Oriented Design?

By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

7 Ways to Assess Semiconductor IP Quality

By Kurt Shuler - 30 Jul, 2015 - Comments: 0

Design teams today are struggling with the quality of semiconductor intellectual property. These teams want first-pass success for SoC creation, but that is becoming increasingly difficult to achieve—especially with highly configurable IP. Yet the more configurable the IP is, the more desirable it is as a differentiator. And if not developed correctly, it may be even more risky than non-confi... » read more

Executive Insight: Grant Pierce

By Ed Sperling - 27 Jul, 2015 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to talk about the effects of industry consolidation, China's impact, and the unfolding security threat with the IoT. What follows are excerpts of that interview. SE: Consolidation is one of the big stories right now. What does that mean for your company and the industry as a whole? Pierce: It's a very inter... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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