tag: noise

Why Do You Need Chip-Package-System Co-Design And Co-Analysis?
By Youngsoo Lee - 13 Oct, 2016 - Comments: 0

Whether it is the need for sustainable energy, or driving performance while keeping power at bay, or enabling safe and reliable operation of any electronic system, containment of electronic noise — power and signal noise is critical to all of the above. Other factors that impact safe and reliable operation are electromigration (EM), electromagnetic interference (EMI) and mechanical stress ena... » read more

Noise Killed My Chip
By Brian Bailey - 08 Sep, 2016 - Comments: 0

In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

Building A Better Resonator
By Katherine Derbyshire - 19 May, 2016 - Comments: 0

The resonant frequency of a beam depends on the mass and stiffness of the beam. Resonance has always been important in the design of musical instruments and amplification systems, as well as the design of bridges and buildings. With the advent of MEMS fabrication techniques, though, came the ability to create very small beams, in the micron or nanometer size range, with resonant frequencies ... » read more

SCREAMER: A Demonstrator Chip For Spectral Noise Optimization By Clock Latency Scheduling
By Teklatech - 13 Apr, 2016 - Comments: 0

This paper outlines the design and measurement of a 130 nm test chip named SCREAMER for reducing the digital switching noise in synchronous circuits. Clock latency scheduling has been investigated as a means to optimize switching noise in the frequency domain through PDN simulation. Integrated in parallel on the chip are four instances of a test design, each addressing a distinct strategy of cl... » read more

Working With FinFETs
By Binu Abraham - 11 Feb, 2016 - Comments: 0

One of the key technology trends driving semi-conductor industry is the adoption of finFET processes. As opposed to a traditional planar transistor, the finFET has an elevated channel or “fin,” which the gate wraps around. Due to their structure, finFETs generate much lower leakage power and allow greater device density. Compared to planar transistors, finFET operate at a lower voltage and ... » read more

Full-Circuit ADC Verification With Analog FastSPICE
By Mentor, a Siemens Business - 14 Oct, 2015 - Comments: 0

Analog to Digital Converters (ADCs) are critical components in high-speed, high-resolution applications where an analog or RF signal has to be processed, stored, or transported in digital form. ADC performance requirements vary by application and include resolution, dynamic range, linearity, power consumption, speed, bandwidth, SNDR (Signal-to-Noise and Distortion Ratio), and ENOB (Effective Nu... » read more

Tackling RF Desense Challenges At The Source
By Margaret Schmitt - 14 Aug, 2015 - Comments: 0

Just imagine you are stepping out of the electronics store with your brand new smart phone. You eagerly scroll down your contacts to dial your best friend and proudly tell them the great news, but as soon as they pick up, your reception is gone! What happened? This problem is commonly described as desense, a degradation of the sensitivity of the receiver due to external noise sources. Desens... » read more

Signal Integrity Issues
By Ed Sperling - 15 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

Optimizing Analog For Power At Advanced Nodes
By Ann Mutschler - 09 Oct, 2014 - Comments: 0

As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

System-Aware SoC Power, Noise And Reliability Sign-off
By Ansys - 08 Oct, 2014 - Comments: 0

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

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