tag: NVM

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences
By Various Writers - 13 Oct, 2021 - Comments: 0

Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

New Memories Add New Faults
By Bryon Moyer - 07 Sep, 2021 - Comments: 1

New non-volatile memories (NVM) bring new opportunities for changing how we use memory in systems-on-chip (SoCs), but they also add new challenges for making sure they will work as expected. These new memory types – primarily MRAM and ReRAM – rely on unique physical phenomena for storing data. That means that new test sequences and fault models may be needed before they can be released t... » read more

FeFETs Bring Promise And Challenges
By Bryon Moyer - 17 Feb, 2021 - Comments: 3

Ferroelectric FETs (FeFETs) and memory (FeRAM) are generating high levels of interest in the research community. Based on a physical mechanism that hasn’t yet been commercially exploited, they join the other interesting new physics ideas that are in various stages of commercialization. “FeRAM is very promising, but it's like all promising memory technologies — it takes a while to get b... » read more

Moving Data And Computing Closer Together
By Bryon Moyer - 09 Jul, 2020 - Comments: 2

The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

NVM Reliability Challenges And Tradeoffs
By Bryon Moyer - 13 Apr, 2020 - Comments: 0

This second of two parts looks at different memories and possible solutions. Part one can be found here. While various NVM technologies, such as PCRAM, MRAM, ReRAM and NRAM share similar high-level traits, their physical renderings are quite different. That provides each with its own set of challenges and solutions. PCRAM has had a fraught history. Initially released by Samsung, Micron, a... » read more

What Is DRAM’s Future?
By Bryon Moyer - 09 Apr, 2020 - Comments: 0

Memory — and DRAM in particular — has moved into the spotlight as it finds itself in the critical path to greater system performance. This isn't the first time DRAM has been the center of attention involving performance. The problem is that not everything progresses at the same rate, creating serial bottlenecks in everything from processor performance to transistor design, and even the t... » read more

Inside The New Non-Volatile Memories
By Bryon Moyer - 07 Apr, 2020 - Comments: 0

The search continues for new non-volatile memories (NVMs) to challenge the existing incumbents, but before any technology can be accepted, it must be proven reliable. “Everyone is searching for a universal memory,” says TongSwan Pang, Fujitsu senior marketing manager. "Different technologies have different reliability challenges, and not all of them may be able to operate in automotive g... » read more

PCIe 5.0 Drill-Down
By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

Taming Novel NVM Non-Determinism
By Bryon Moyer - 10 Mar, 2020 - Comments: 1

New memory technologies may have non-deterministic characteristics that add calibration to the test burden — and may require recalibration during their lifetime. Many of these memories are in development as a result of the search for a storage-class memory (SCM) technology that can bridge the gap between larger, slower memories like flash and faster DRAM memory. There are several approache... » read more

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