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FeFETs Bring Promise And Challenges

New technology could have an impact on NVM, in-memory processing, and neuromorphic computing.

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Ferroelectric FETs (FeFETs) and memory (FeRAM) are generating high levels of interest in the research community. Based on a physical mechanism that hasn’t yet been commercially exploited, they join the other interesting new physics ideas that are in various stages of commercialization.

“FeRAM is very promising, but it’s like all promising memory technologies — it takes a while to get beyond promising,” said Rob Aitken, fellow and director of technology on the research team at Arm. “It has the potential to have better benefits than the other new non-volatile memory (NVM) technologies that are on the table today.”

Ferroelectric behaviors are opening up opportunities for non-volatile memory, combined logic/memory functions, and neuromorphic modeling. While it’s still early days for the technology, developers are cautiously optimistic about its future.

Ferroelectricity
A ferroelectric material has a crystalline structure such that charges don’t balance to zero around a central point, which gives it an electrical dipole. The dipoles originate in small domains within the crystal, making it possible for the bulk material to look more or less ferroelectric. The more domains are aligned, the stronger the overall net dipole will be.

“Ferroelectrics is atomic movement where, in a crystal structure, an atom can move between two stable spots, back and forth,” said Greg Yeric, CTO of Cerfe Labs. “If you get enough of them to move, you create a dipole, and that’s the ferroelectric memory effect. There is a minute, femtometer change in the lattice between the two states. To be quite honest, I think it’s a theoretical change more than it has ever been measured.”

The benefit of this dipole is that it can be coerced in one direction or the other, giving two states. While it can be used digitally in that fashion, the fact that it can have a large or small dipole also makes the phenomenon useable in an analog manner, as well.

Fig. 1: A FeFET showing gate (G), source (S), and drain (D). The gray layer is the ferroelectric material, with the arrows indicating dipoles. When fully “programmed,” all of the arrows/domains would be aligned in one direction or the other. Source: IEDM/Purdue University, Rochester Institute of Technology, University of Notre Dame

Fig. 1: A FeFET showing gate (G), source (S), and drain (D). The gray layer is the ferroelectric material, with the arrows indicating dipoles. When fully “programmed,” all of the arrows/domains would be aligned in one direction or the other. Source: IEDM/Purdue University, Rochester Institute of Technology, University of Notre Dame

PZT is a popular piezoelectric material, but it can’t be used for FeFETs. “It’s a good ferroelectric material, but it is intrusive to the fab and is not logic-friendly,” observed Ali Pourkeramati, CEO of FMC. So while it has been used in pure memories, there appear to be no efforts to incorporate it into CMOS circuits.

But a number of other materials have been evaluated, and one in particular is gaining momentum — hafnium oxide (HfO2 — also referred to as hafnia in some papers). “PZT loses its ferroelectric properties when scaled to very thin layers,” said Dr. Stefan Müller, CTO of FMC. “This is where ferroelectric HfO2 actually obtains its ferroelectric properties.”

The voltages required to flip the dipole depend strongly on the materials used. Some papers discuss voltages as high as 20 volts. Others have much lower voltages. “It’s different material systems with different polarizations over different thicknesses,” noted Sven Beyer, deputy director, technology and integration, eNVM at GlobalFoundries. “2 to 5 volts is the range where we are working. If you go lower, you get into disturb [issues], and 5 volts is usually something that a lot of chips have [for I/Os].”

Ferroelectric transistors can be used for both memory and logic. Implementing logic using FeFETs is a significant topic in its own right, so the following will focus on the memory implementations, since they’re where most of the development focus is. Logic will be covered at a future time.

Hafnium oxide as ferroelectric material
Hafnium oxide is a familiar substance in the CMOS fab. “It has been around for a long time as the high-Κ gate material for CMOS logic, and the memory companies used it for DRAM,” said Pourkeramati. “Qimonda (a now-defunct DRAM maker) accidentally overheated it, and they found that when they annealed it, it goes from amorphous to crystallized and becomes ferroelectric.”

Fig. 2: Ferroelectric HfO2 constrasted with amorphous HfO2 and crystalline ZrO2. Source: FMC

As a pure substance, it’s typically not ferroelectric. It can be made ferroelectric, however, if the crystal lattice is strained. “The primary purpose of doping in ferro NVM is to induce ferroelectricity via stress,” said Yeric. “There is a tight window with ferro — the film has to be very thin so that the stress can induce sufficient ferroelectricity, but when very thin, you run into stability issues.”

The underlying notions can apply to other materials, as well, although the specifics may vary. Hafnium oxide happens to be a familiar, fab-friendly material, which dramatically lowers the barrier to acceptance if all other anticipated behaviors are borne out during development.

“Hafnium oxide reduces the gap between the non-volatile memory process and the CMOS logic process,” noted Pourkeramati. “Hopefully, in a few years, we can be at the same node as the logic guys, and NVM and logic will be developed at the same time.”

Material changes are challenging for chip manufacturing. “The hafnium thing is really good, because it doesn’t introduce materials into the fab that are worrisome,” said Jim Handy, memory analyst at Objective Analysis. “But it does have this issue of requiring a version of hafnium oxide that still needs to be better understood.”

It turns out that hafnium oxide can have three different crystalline arrangements depending on what other dopants are added. One popular dopant is zirconium, making so-called HZO a frequent compound in FeFET research. But the amount of zirconium used makes a critical difference.

Too little, and the crystal structure is “monoclinic,” with no net dipole. Too much, and the structure is “tetragonal,” again with no net dipole. In the middle, the structure is “orthorhombic,” and it is in this phase that the material becomes ferroelectric. “This technology becomes 50% zirconium and 50% hafnium, plus the oxygen,” said Pourkeramati.

Fig. 3: The annealing and zirconium quantity have a strong impact on the crystal arrangement. Source: FMC

Fig. 3: The annealing and zirconium quantity have a strong impact on the crystal arrangement. Source: FMC

While most projects appear to have used doping to make the material ferroelectric, there has also been success sputtering it in a particular fashion (the details of which aren’t public) so that the undoped material ends up ferroelectric. In general, doping, deposition technique, layer thickness, and anneal cycles appear to be critical to successfully creating the ferroelectric phase. FMC sees lower performance with pure HfO2, however. “We can use the hafnium oxide without anything, but then it limits our endurance,” said Pourkeramati.

Cerfe Labs is working on a FeFET technology. While the company is using HfO2, it is not relying on strain to achieve ferroelectricity. “There are some fundamental limitations with the strained HfO2 approach,” said Yeric. The company has not announced its technology yet, so there is little information available.

The thickness also plays a part in how the material works. We’ve seen that hafnium oxide layers have to be thin to achieve ferroelectric characteristics. But if they’re very thin (1.5 to 3nm), they work as simple non-hysteretic switches. Relatively thicker versions (5 to 10nm) can be used for multi-level cells, since there’s more room for a richer mix of polarization domains.

Combining FeFETs and logic
Things get more difficult when trying to integrate FeFETs with other CMOS logic, because the FeFET processing must be compatible with the rest of the circuit. “Co-integrating it is tricky,” said Beyer. “It comes down to the details of what kind of dopants you can put in there, what kind of temperature budgets you can have, what kind of strain you have to deal with.”

FMC claimed to have a process that differs little from standard CMOS for doping the HfO2 into HZO. “We have, at maximum, two extra masks,” said Pourkeramati. “The only change between the hafnium-oxide transistors and ours is the titanium nitride [electrode] that that creates the interface between the hafnium oxide and the poly. The rest is going to be the same.” GlobalFoundries has been working with FMC to develop a manufacturing path, and they claimed that they’re the first to successfully integrate FeFETs with CMOS.

Because a single bad memory cell can ruin an entire array, the statistics have to work as well. 1% failures would result in 0% yield. The effects of variation in doping and internal stresses matter, especially when the resulting changes in VT result in signals that are near or below threshold. FMC said that it’s not so bad and that they’re addressing it, with more to say on that in the future.

There are questions regarding temperature stability. “The atom positioning dance means FeRAM will struggle with high temperatures,” said Yeric. FMC, however, claimed their technology to be very stable. “The temperature stability will be between 4 K up to 700 K,” claimed Pourkeramati. “No other available technology can have that stability.”

In addition, the performance FMC and GlobalFoundries promise appears attractive, although speed expectations for FeFETs vary widely. “Our read speed is less than 25 ns, and it can be faster,” said Pourkeramati. “Our write speed can be as fast as read. Due to our setup and testing vehicle, we are getting less than 1 µs, but it will be sped up.”

Some of this range of opinions on speed may tie to the supply voltage. “At >4.5 V, you can switch in the 10 ns regime. In the millisecond range, you can go as low as <3 V,” said Beyer. “Theoretically, you should be able to get down to 1 ns using an internal clock.”

In addition, a FeFET’s drive can be tuned in a way that other NVM cells cannot. “The FeFET is not a stiff memory cell, but rather a flexible transistor with two VTs,” Beyer explained. “Hence you can scale width and length to get high drive currents. Read-speed is dependent on drive current.”

Other FMC metrics also look promising. “We are going all the way down to the 10-15 joules/bit for writing, and, for cell area, 10F²” added Pourkeramati. That compares to 60F2 for other NVM.

Here again, others are more cautious. “FeRAM will never be as fast as MRAM/SRAM, and it will be challenged to scale aggressively in dimension,” said Yeric.

It appears that FeFETs will scale to advanced nodes. “We have demonstrated FeFET behavior on finFETs,” said Steven Soss, distinguished member of technical staff, differentiated technology research at GlobalFoundries. There’s also no fundamental issue expected with gate-all-around transistors.

Fig. 4: FeFETs implemented on planar (left), finFET (center), and gate-all-around (right) structures. Source: FMC

Fig. 4: FeFETs implemented on planar (left), finFET (center), and gate-all-around (right) structures. Source: FMC

From a competitive standpoint, FMC seems to be laying down a legal gauntlet. “We have the fundamental right to the fundamental patents,” said Pourkeramati.

Self-selecting memory
While numerous materials are vying to be the next great NVM cell, FeFETs have one major advantage. Other cells have two terminals and require an additional selector transistor to ensure that leakage through one cell doesn’t disturb another cell. These selector transistors are typically laid out next to the memory cell and therefore take up more space (with the possible exception of a new vertical selector being developed by Spin Memory).

A FeFET cell, on the other hand, is a three-terminal device, so it can be its own selector, eliminating the need for the additional device and allowing for a more compact memory array. Alternatively, ferroelectric tunnel junctions (FTJs) are simple two-terminal capacitors that can be programmed in one of two states, but may again need a selector of some sort.

Fig. 5: A 3D FTJ stack for use in in-memory computing. Source: IEDM/Kioxia

Fig. 5: A 3D FTJ stack for use in in-memory computing. Source: IEDM/Kioxia

“Give me an FTJ as a perfect binary switch, and you’re going to have leakage,” said Lucian Shifren, vice president of research at Cerfe Labs. “The only reason to have a selector is leakage.” He also sees them as tricky components. “The problem with tunnel junctions, in general — and you can see this in MTJs – is that they’re fickle. They usually require really advanced heterostructures, with very thin materials.”

While it’s possible to build these transistors along with the standard operational transistors as a front-end-of-line (FEOL) process, others are experimenting with building them on the back-end (BEOL) so that they can be stacked vertically into 3D memories on top of the logic below. Here in particular, the process would need not to interfere with the delicate balances achieved during FEOL manufacturing.

That runs counter, however, to what some believe one of the benefits of FeRAM to be. Most new NVM technologies are made in the back-end of line (BEOL) of the process, placing them atop the silicon stack. “The BEOL NVMs have a downside in blocking the metal routing for other purposes,” said Yeric.

FeFETs can be built in the front-end of line (FEOL), which gets them out of the way of upper-level metal, while moving the challenge down to the lower metal layers. So there’s a tradeoff between where the cells sit and the ability to stack them into a 3D memory, which requires BEOL placement.

Analog memory, neuromorphic applications, and other ideas
The use of a FeFET as a memory cell has another dimension. Because it can take on partial states between “high” and “low,” it can be used as an analog cell in in-memory computing structures for AI. In that case, the cell would have a static value that’s determined by the model in advance. The only reason that value would be changed would be if the model were updated, with new weight values being loaded in.

More than one IEDM paper covered this application. In one example1, a team from the Univ. of Notre Dame and Georgia Tech highlighted a preference for a BEOL stacked implementation. “When we go to this monolithic 3D CIM (compute-in-memory) architecture, then we can place these memory areas in the back-end of line and stack them up on top of the CMOS peripheral circuitry, which is now underneath,” said Sourav Dutta, a research associate at the University of Notre Dame. “Such a monolithic architecture can provide a significant area, energy, and latency advantage.”

Fig. 6: A stacked 3D memory for storing synaptic weights in an in-memory compute application. Source: IEDM/Univ. of Notre Dame, Georgia Tech

Fig. 6: A stacked 3D memory for storing synaptic weights in an in-memory compute application. Source: IEDM/Univ. of Notre Dame, Georgia Tech

Another paper2 by a team from Bosch, Fraunhofer, and TU Kaiserslautern, discussed a FeFET approach that on the surface looks more like the one being taken by other novel NVM technologies, which have a cell consisting of a transistor (for selecting) and a resistor (the programmable element), or a 1T1R cell. A variant on this was proposed where the 1T is the FeFET itself, acting both as selector and programmable storage. But rather than having a resistor for each cell, there’s one resistor for a segment of the array whose purpose is to reduce current variability.

“Connected with the high Ion/Ioff ratio is a large variability in the IDS of the low-VT state even for a very small VT variation. To compensate for the IDS variation, we suggest to form a 1FeFET1R (1F1R) bit cell,” the paper noted.

Fig. 7: A FeFET memory array segment with a single resistor (Ω) for reducing current variability. Source: IEDM/Bosch, Fraunhofer, TU Kaiserslautern

Fig. 7: A FeFET memory array segment with a single resistor (Ω) for reducing current variability. Source: IEDM/Bosch, Fraunhofer, TU Kaiserslautern

But beyond that, the ability to program the cell incrementally has caught the eye of researchers working on neuromorphic computing. Assuming good cell data retention, this can act as an integrate-and-fire element, desirable for spiking and other neuromorphic neural networks. The idea is that “spikes,” or events of one sort or another, could incrementally add or subtract from the polarized state of the cell in real time, driving decisions based on the cell achieving some high state of polarization in one direction or the other.

“You can take a 1-µs pulse and divide it into 10 pulses of 100 ns and put even one second in between,” said Beyer. If a leaky version were desired, that could be engineered in. “You can intentionally kill retention. And then you can design in your leaky part.”

There’s also a fair bit of interest in exploring the use of FeFETs in creating content-addressable memories (CAMs). At this point, such work reflects research projects, not commercial efforts. An IEDM paper³ by a team from Zhejiang University, Fraunhofer Institute for Photonic Microsystems, UC Irvine, and Rochester Institute of Technology, described a very low-power CAM that could handle approximate matches.

“This CAM design is very compact because it has only two FeFETs. it’s also has very low energy and delay because it’s a very compact structure, and you do not need to supply high current to write,” said Li in his IEDM presentation.

Fig. 8: A two-FeFET CAM cell. Source: IEDM/Zhejiang Univ., Fraunhofer, UC Irvine, Rochester Institute of Technology

Fig. 8: A two-FeFET CAM cell. Source: IEDM/Zhejiang Univ., Fraunhofer, UC Irvine, Rochester Institute of Technology

There is even interest in using FeFETs for volatile memory applications. “It has the potential for endurance that puts it in the realm of something that we can use as a substitute for volatile memories of various sorts,” said Arm’s Aitken.

Reality check: significant challenges remain
While there’s lots of interest in FeFETs, much remains to be worked out, as evidenced by the enormous number of FeFET-related papers at the recent IEDM conference. The low-level physical mechanisms appear to be more complex than would be initially expected. That’s based on some otherwise puzzling behaviors that show that programming the cell isn’t the simple thing it appears to be. Data retention has been a problem, as well as a cell-state trajectory that seems to morph over time after the initial programming event.

One of the areas of focus relates to charge traps at one of the interfaces between the hafnium oxide and the top gate metal. It appears that charges are first trapped and then eventually released over time. It would be easiest if any such behaviors could be eliminated, but at the very least they would need to be understood and predictable so that developers could design around it.

Another idea from an Intel team4 at IEDM was to back-gate the hafnium oxide. “Whenever we create a top-gated ferroelectric device, we deposit the ferroelectric on top of the semiconductor channel,” said Ankita Sharma, currently senior product marketing manager at Nvidia, and a former Intel executive. “Oftentimes, this results in an unintended formation of an interface [damage] layer. This interface layer can interfere with the signal that comes out of the ferroelectric FET, as well as affecting other parameters associated with endurance, cycling, and retention.” In the back-gated version, the material is deposited onto a clean surface rather than being etched from above.

Fig. 9: A more traditional approach creates an interface layer between the ferroelectric material and the channel. Using a back-gate instead can eliminate that layer and its associated traps. Source: IEDM/Intel

Fig. 9: A more traditional approach creates an interface layer between the ferroelectric material and the channel. Using a back-gate instead can eliminate that layer and its associated traps. Source: IEDM/Intel

Other studies look at some of the behaviors during programming. At the micro level, researchers are looking at the dynamics associated with writing data. In one case5, they’re looking at “percolation” — the gradual switching of small domains in isolation until a consistent polarization “path” makes its way through the full thickness of the material.

Fig. 10: “Percolation” refers to the gradual establishment of microdomains until they connect up into a path from source to drain. Source: IEDM/KU Leuven, Imec

Fig. 10: “Percolation” refers to the gradual establishment of microdomains until they connect up into a path from source to drain. Source: IEDM/KU Leuven, Imec

The fundamental physical phenomenon driving FeFETs is called “remanent polarization,” or PR. “If we want to have devices being programmed to a low VT, we need to make sure that the + PR domain population can connect from the source all the way to the drain, such that there will be a continuous inversion path in the channel,” said Imec researcher Yang Xiang during the IEDM presentation. “And this connectivity is exactly what percolation is about.”

Another study by a team6 from Purdue University, Rochester Institute of Technology, and the University of Notre Dame looked at the creation of these domains, with initial formation dominated by nucleation of independent sites until enough build up to where further progress involves the “walls” moving to complete the change of polarization.

Fig. 11: Early on, nucleation dominates (the small bumps). Then the walls move left or right to close out the space (lower levels, left and right). Source: IEDM/Purdue University, Rochester Institute of Technology, University of Notre Dame

Fig. 11: Early on, nucleation dominates (the small bumps). Then the walls move left or right to close out the space (lower levels, left and right). Source: IEDM/Purdue University, Rochester Institute of Technology, University of Notre Dame

Going to market
It can be confusing to understand just where this technology stands when it comes to commercial production. Companies like FMC are very bullish on what they have working, claiming to have addressed the trapping issues. But work remains, and even they don’t see full release until 2023 or 2024.

It’s also hard to gauge the industry excitement at this point. On the one hand, based on the amount of research being done, there appears to be very strong interest in getting this to work. On the other hand, there is a significant punch-list of things that must be addressed before this will be ready for market. It’s likely that we’ll be watching things evolve for a few more years before the final verdict comes in.

“It’s a very complicated material system that that has a very narrow window of operation,” said GlobalFoundries’ Soss. “But it is a very interesting memory that we are watching very closely to see how it how it evolves.”

Notes:

  1. “Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory”, Dutta et al, Univ. of Notre Dame, Georgia Tech, IEDM 2020
  2. “Ultra-Low Power Flexible Precision FeFET Based Analog In-Memory Computing”, Soliman et al, Bosch, Fraunhofer, TU Kaiserslautern, IEDM 2020
  3. “A Scalable Design of Multi-Bit Ferroelectric Content Addressable Memory for Data-Centric Computing”, Li et al, Zhejiang Univ., Fraunhofer, UC Irvine, Rochester Institute of Technology, IEDM 2020
  4. “High Speed Memory Operation in Channel-Last, Back-gated Ferroelectric Transistors”, Sharma et al, Intel, IEDM 2020
  5.  “Implication of Channel Percolation in Ferroelectric FETs for Threshold Voltage Shift Modeling”, Xiang et al, KU Leuven, Imec, IEDM 2020
  6. “Ferroelectric Thickness Dependent Domain Interactions in FEFETs for Memory and Logic: A Phase-field Model based Analysis”, Saha et al, Purdue University, Rochester Institute of Technology, University of Notre Dame, IEDM 2020

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3 comments

Michael Williams says:

Thanks for the article! I may not understand all of the material presented here but none the less I try to!
Articles like yours helps me to stay well informed regarding the state of the art in device physics and implementation of new devices!

Raj says:

Thanks for the very informative article on an emerging new non volatile memory technology. The MRAM, FeRAM and PCRAM are the future potential memory technologies that could pave a way for the development of a universal memory technology.

Xtn says:

Great to see this coming back after 25 years – and with lots of new ideas.
Thanks – nice summary.

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